Abstract: A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

Abstract: A method for fabricating an electronic component with a self-aligned source, drain and gate. The method includes forming a dummy gate on a silicon substrate, in which the dummy gate defines a position for a channel of the component. The method also includes at least one implantation of doping impurities in the substrate, to form a source and a drain on either side of the channel, using the dummy gate as an implanting mask, superficial, self-aligned siliciding of the source and drain, depositing at least one contact metal layer having a total thickness greater than a height of the dummy gate, polishing the at least one contact metal layer stopping at the dummy gate, and replacing the dummy gate by at least one final gate separated from the substrate by a gate insulating layer, and electrically insulated from the source and drain.

Abstract: A method for forming a metal wiring layer in a semiconductor device using a dual damascene process is provided. A stopper layer, an interlayer insulating layer, and a hard mask layer are sequentially formed on a semiconductor substrate having a conductive layer. A first photoresist pattern that comprises a first opening having a first width is formed on the hard mask layer. The hard mask layer and portions of the interlayer insulating layer are etched using the first photoresist pattern as an etching mask, thereby forming a partial via hole having the first width. The first photoresist pattern is removed. An organic material layer is coated on the semiconductor substrate having the partial via hole is formed to fill the partial via hole with the organic material layer. A second photoresist pattern that comprises a second opening aligned with the partial via hole and having a second width greater than the first width is formed on the coated semiconductor substrate.

Abstract: A semiconductor laser device includes a resonant cavity formed on a GaAs substrate, the resonant cavity including a quantum well (QW) active layer structure having a GaInNAs(Sb) well layer and a pair of barrier layers. The QW structure has a conduction band offset energy (?Ec) equal to or higher than 350 milli-electron-volts (meV) between the well layer and the barrier layers, and each of the barrier layers a tensile strain equal to or lower than 2.5%.

Abstract: A semiconductor device includes first and second gate electrode, first and second gate insulating film, semiconductor layer, source and drain regions, and source and drain electrodes. The first gate electrode is formed in the insulating film. The first gate insulating film is formed on the first gate electrode. The semiconductor layer is formed on the insulating film. The source and drain regions are formed in the semiconductor layer. The source and drain electrodes are respectively formed on the source and drain regions. The positions of side wall surfaces of the source and drain electrodes which face each other are substantially aligned with the positions of both side wall surfaces of the first gate electrode in a direction perpendicular to the surface of the insulating film. The second gate insulating film is formed on the semiconductor layer. The second gate electrode is formed on the second gate insulating film.

Abstract: An embodiment of the instant invention is a method of oxidizing a first feature (feature 108 and/or feature 104 of FIG. 1 and feature 314 of FIG. 3) while leaving a second feature substantially unoxidized (features 110 and 112 of FIG. 1 and features 310 and 312 of FIG. 3), the method comprised of subjecting the first and second features to an oxygen-containing gas and a separate hydrogen-containing gas. Preferably, the oxygen-containing gas is comprised of gas selected from the group consisting of O2, N2O, CO2, H2O, and any combination thereof, and the hydrogen-containing gas is comprised of H2. The first feature is, preferably, comprised of polycrystalline silicon, silicon oxide, or a dielectric material, and the second feature is, preferably, comprised of tungsten.

Abstract: After forming a resist pattern on an insulating film deposited on a semiconductor substrate, the insulating film is subjected to plasma etching using an etching gas including carbon and fluorine with the resist pattern used as a mask. A polymer film having been deposited on the resist pattern during the plasma etching is subjected to a first stage of ashing with a relatively low chamber pressure and relatively low plasma generation power by using an oxygen gas or a gas including oxygen as a principal constituent. A residual polymer present on the insulating film in completing the first stage of the ashing is subjected to a second stage of the ashing with a relatively high chamber pressure and relatively high plasma generation power by using an oxygen gas or a gas including oxygen as a principal constituent.

Abstract: A semiconductor device includes a multiplayer substrate with a cavity, a semiconductor chip in the cavity, wiring lines with lands, a cover of a material, covering the semiconductor chip and having a protruding part, and chips bonded to the wirings lines with a solder having a low melting point. The protruding part has a height from the surface of the multiplayer substrate greater than the thickness of the wiring layer.

Abstract: There is provided a substrate for information recording media and a manufacturing method thereof, which allow an information recording medium to be driven reliably and stably even when the flying height is made lower than conventionally to cope with increased recording density of the data zone. Precision polishing is carried out on a glass substrate using a polishing agent. After the precision polishing, surface treatment is carried out using an etching liquid containing both hydrofluoric acid and a fluoride salt.

Abstract: A dual damascene process for producing interconnects. A dielectric layer is formed over the surface of a semiconductor substrate which comprises conductive layers or MOS devices. The dielectric layer is patterned to form trench openings and a metal layer is deposited over the dielectric layer to fill the plurality of trenches. A photoresist layer is formed over the metal layer and defined to form via hole patterns above the trenches. The metal layer and the dielectric layer are etched with the patterned photoresist layer as a mask to form a plurality of via holes exposing the underlying conductive layer or MOS devices and a dual damascene opening is formed.

Abstract: A process of eliminating resist footing on a hardmask when preparing a semiconductor wafer stack, comprising: a) depositing a layer of hardmask material on a substrate; b) subjecting the hardmask to oxygen under conditions sufficient to produce an oxide cap layer and provide a hardmask/oxide cap layer with a substrate reflectivity below 0.8%; c) forming a layer of SiO2 on the hardmask/oxide cap layer; d) forming a layer of photoresist on the layer of SiO2; e) patterning and developing the layer of photoresist by exposing photoresist; and f) etching exposed portions of the layer of hardmask/oxide cap layer/SiO2 layer to obtain a semiconductor wafer stack with no standing waves and free from resist footing.

Abstract: The invention includes a hermetic container provided with a substrate mount; a vacuum exhauster connected to the hermetic container; a current member; and a current member raising and lowering mechanism. When the current member is raised and lowered as a function of the pressure inside the hermetic container, a liquid flow of the coating solution on the substrate is controlled, thereby controlling the uniformity of the film thickness of the coating solution.

Abstract: A method of forming a dielectric film composed of metal oxide under an atmosphere of activated vapor containing oxygen. In the method of forming the dielectric film, a metal oxide film is formed on a semiconductor substrate using a metal organic precursor and O2 gas while the semiconductor substrate is exposed under activated vapor atmosphere containing oxygen, and then, the metal oxide film is annealed while the semiconductor substrate is exposed under activated vapor containing oxygen. The annealing may take place in situ with the formation of the metal oxide film, at the same or substantially the same temperature as the metal oxide forming, and/or at at least one of a different pressure, oxygen concentration, or oxygen flow rate as the metal oxide forming.

Abstract: An asymmetric field effect transistor (FET) that has a threshold voltage that is compatible with current CMOS circuit designs and a low-resistance gate electrode is provided. Specifically, the asymmetric FET includes a p-type gate portion and an n-type gate portion on a vertical semiconductor body; an interconnect between the p-type gate portion and the n-type gate portion; and a planarizing structure above the interconnect.

Abstract: A MOS transistor with a drain extension includes an isolation block on the upper surface of a semiconductor substrate. The isolation block has a first sidewall next to the gate of the transistor, and a second sidewall that is substantially parallel to the first sidewall. The isolation block further includes a drain extension zone in the substrate under the isolation block, and a drain region in contact with the drain extension zone. The drain region is in the substrate but is not covered by the isolation block.

Abstract: A semiconductor device having: an underlie having a conductive region in the surface layer of the underlie; an insulating etch stopper film covering the surface of the underlie; an interlayer insulating film formed on the insulating etch stopper film; a wiring trench formed in the interlayer insulating film, the wiring trench having a first depth from the surface of the interlayer insulating film; a contact hole extending from the bottom surface of the wiring trench to the surface of the conductive region; and a dual damascene wiring layer embedded in the wiring trench and the contact hole, wherein the interlayer insulating film includes a first kind of an insulating layer surrounding the side wall and bottom surface of the wiring trench and a second kind of an insulating layer having etching characteristics different from the first kind of the insulating layer.

Abstract: Disclosed is a process of treating semiconductor substrates, including the production of pure water, a method of producing the pure water for semiconductor fabrication, and a water-producing apparatus. Ammonia is catalytically oxidized in a catalytic conversion reactor to form pure water. The water is then supplied to a semiconductor fabrication process. The water-producing apparatus comprises a housing surrounding a catalytic material for adsorbing ammonia, an ammonia and oxidant source, each in communication with the housing, and an outlet for reaction products. The outlet is connected to a semiconductor processing apparatus. According to preferred embodiments of the invention, the apparatus can be a catalytic tube reactor, a fixed bed reactor or a fluidized bed reactor.

Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.

Abstract: A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450° C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.

Abstract: A field effect transistor has source 12, body 10 and drain 8 formed on an insulating layer 4. Implant regions 40 are implanted under the source 12, laterally aligned with the source 12 by implantation through opening in the source mask. The ruggedness of the transistor may thereby be improved without affecting the doping in channel region 19.