Abstract: A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and second transistor source/drain regions are formed on the substrate adjacent to opposite sides of the gate electrodes. N-type impurities, preferably phosphorous atoms, are then implanted into the first source/drain region which will serve as the capacitor buried contact.

Abstract: A method of manufacturing an integrated circuit is provided having a semiconductor wafer. A chemical-mechanical polishing stop layer is deposited on the semiconductor wafer and a first photoresist layer is processed over the chemical-mechanical polishing stop layer. The chemical-mechanical polishing stop layer and the semiconductor wafer are patterned to form a shallow trench and a shallow trench isolation material is deposited on the chemical-mechanical polishing stop layer and in the shallow trench. A second photoresist layer is processed over the shallow trench isolation material leaving the shallow trench uncovered. The uncovered shallow trench is then treated to become a chemical-mechanical polishing stop area. The shallow trench isolation material is then chemical-mechanical polished to be co-planar with the chemical-mechanical stop layer and the chemical-mechanical polishing stop treated area.

Abstract: A method for preventing a diffused reflection from being generated in patterning a via hole for the metal interconnection is disclosed. The disclosed method includes: forming an insulation layer on a semiconductor substrate, wherein elements for operating a semiconductor device are formed on the semiconductor substrate; forming first photoresist patterns on the insulation layer; etching the insulation layer in order to form a first via hole using the first photoresist patterns and then forming a resulting structure; coating a first anti-reflecting coating layer on the resulting structure with a low viscosity; coating a second anti-reflecting coating layer on the resulting structure with a low viscosity; forming second photoresist patterns on the second anti-reflecting coating layer; and forming a second via hole using the second photoresist patterns.

Abstract: A gate insulating film in a memory cell portion is thicker than a gate insulating film in a peripheral circuitry. Source/drain of an MOS transistor in the memory cell portion have double-diffusion-layer structures, respectively, and source/drain of an MOS transistor in the peripheral circuitry have triple-diffusion-layer structures, respectively.

Abstract: A semiconductor device includes a first insulating layer having a through hole; a first interconnection having a first conductive layer, a first barrier layer, and a first main interconnection; and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, a problem wherein copper in the first main interconnection transfers from a connection portion thereof to the second interconnection due to electromigration, so that a void is formed at the connected portion resulting in the first interconnection being disconnected from the second interconnection, can be prevented.

Abstract: A transistor (10) is formed with a low resistance trench structure that is utilized for a gate (17) of the transistor. The low resistance trench structure facilitates forming a shallow source region (49) that reduces the gate-to-source capacitance.

Abstract: When a through hole 17 is transferred on a pair of contact holes 10 putting a data line DL therebetween, even if a pair of through holes 17 putting the data line DL therebetween are deviated, the pair of through holes are connected to the contact hole 10b and not connected to the data line DL. By this manner, a mask pattern formed by a photomask is use so as to be deviated and disposed in a direction separately from the data line DL at a design stage. This results in improvement of an alignment tolerance of the pattern.

Abstract: A capacitor structure is formed in a window in a dielectric layer of an integrated circuit. The lower electrode (or plate) is disposed on a portion side surface of the cavity but not on the top surface of the dielectric. A layer of dielectric material is disposed on the lower electrode and upon the top surface of the integrated circuit dielectric. Finally, an upper electrode (or plate) is disposed on the layer of dielectric material. Because the lower electrode is removed from a portion of the cavity sidewall and top surface of the dielectric shorting problems which could result during planarization are avoided. A technique for fabricating an integrated circuit (IC) for use in multi-level structures is also disclosed. The technique is readily incorporated into standard multi-level processing techniques. After a window is opened in the particular dielectric layer of the IC, a conductive layer is deposited in the window and forms the lower plate of a capacitor.

Abstract: A low temperature aluminum planarization process. Vias, including high aspect ratio vias, are filled using a liner layer, a seed layer, and a fill layer. The device associated with the via is exposed to a reactive gas prior to applying the fill layer to the device.

Abstract: A semiconductor device having a test mark comprising: a semiconductor substrate; a first TEOS layer formed on the semiconductor substrate; a second TEOS layer formed on the first TEOS layer and having a fluidity lower than that of the first TEOS layer at an elevated temperature; a recess formed in the first and second TEOS layers and exposing the surface of the semiconductor substrate, wherein the horizontal cross section of the recess is substantially rectangular in configuration; and a metal layer formed between the first and second TEOS layers and opposing to the corner of the recess.

Abstract: A method of forming an insulating material for use in an integrated circuit includes providing a substrate of the integrated circuit and forming a polymeric material on the substrate. At least a portion of the polymeric material is converted to a foamed polymeric material. The converting of the polymeric material includes exposing at least a portion of the polymeric material to a supercritical fluid. Further, an integrated circuit includes a substrate of the integrated circuit and a foamed polymeric material on at least a portion of the substrate. The integrated circuit may further include a conductive layer adjacent the foamed polymeric material. The conductive layer may be a metal line on the foamed polymeric material, or the conductive layer may be an interconnect, e.g., a contact or a via, adjacent the foamed polymeric material.

Abstract: A method for depositing tungsten nitride uses a source gas mixture having a silicon based gas for depositing the tungsten nitride to overlie a deposition substrate. A non-planar storage capacitor has a tungsten nitride capacitor electrode.

Abstract: An organic electroluminescent device comprises a pair of electrodes and a layer structure provided between the paired electrodes and including, at least, an emission layer comprising a specific type of oligomer. The layer structure may further comprise an electron injection layer and an electron transport layer, one of which comprises a specific type of oligomer. Alternatively, the layer structure may be of the type which comprises an organic layer having a charge transport interference layer in the inside thereof along with an emission layer.

Abstract: A method of manufacturing a semiconductor device is capable of preventing a dishing phenomenon from occurring without using dummy patterns. A plurality of conductive patterns are formed along the entire surface of a semiconductor substrate with an irregular pattern density. The conductive patterns have a first stopper layer at the top thereof. An interlayer insulating layer is formed on the conductive patterns. Next, a second stopper layer is formed on the interlayer insulating layer. An etching mask is formed on the second stopper layer so as to expose a first region having a conductive pattern density that is higher than that of another region(s). By using the etching mask, the second stopper layer and part of the interlayer insulating layer are etched at the first region.

Abstract: The invention includes a semiconductor construction comprising a semiconductor substrate, and a first layer comprising silicon and nitrogen over the substrate. A second layer comprising at least 50 weight % carbon is over and physically against the first layer, and a third layer consisting essentially of a photoresist system is over and physically against the second layer. The invention also includes methodology for forming the semiconductor construction.

Abstract: A fabrication method of a semiconductor device with a capacitor is provided, which prevents leakage current from increasing and dielectric breakdown resistance from decreasing during a CVD or dry etching process for forming an insulating film to cover the capacitor. In this method, a lower electrode of a capacitor is formed on a first insulating film. The first insulating film is typically formed on or over a semiconductor substrate. A dielectric film of the capacitor is formed on the lower electrode to be overlapped therewith. An upper electrode of the capacitor is formed on the dielectric film to be overlapped therewith. A second insulating film is formed to cover the capacitor by a thermal CVD process in an atmosphere containing no plasma at a substrate temperature in which hydrogen is prevented from being activated due to heat.

Abstract: Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second capacitor such that at least a portion of the second capacitor is underlying the first capacitor. Such memory cell capacitors can thus have increased surface area for a given capacitor height versus memory cell capacitors formed strictly laterally adjacent one another. The memory cell capacitors can be fabricated using silicon-on-insulator (SOI) techniques. The memory cell capacitors are useful for a variety of memory arrays, memory devices and electronic systems.

Abstract: A local interconnect structure that includes a silicon spacer. After deposition of polysilicon gates and formation of spacers on a semiconductor substrate, photolithography and oxide etch steps are performed to remove a portion of a spacer along a segment of the gate where local interconnection is to be formed. A thin screen oxide layer is deposited over the wafer, followed by the formation of diffusion regions. A silicon layer (either amorphous or polycrystalline) is then deposited. The silicon layer is then selectively etched so as to form a silicon spacer along the segment of the gate where local interconnection is to be formed. A conventional SALICIDE process is performed, leading to simultaneous silicidation of the diffusion region, the gate, and the silicon spacer. The resulting local interconnect electrically connects the gate and the diffusion region.

Abstract: Methods are provided for forming a die package. The method comprises stiffening a flexible substrate to provide a first flexibility of the flexible substrate, forming a mounting element on a first side of the flexible substrate, and mounting a first die on the first side of the flexible substrate to couple the first die to the mounting element. Further, the method comprises mounting a second die on a second side of the flexible substrate and mounting a third die on the second side of the flexible substrate to couple the second and third die to the mounting element, respectively. Furthermore, the method comprises adjusting the stiffening to provide a second flexibility of the flexible substrate that is greater than the first flexibility, and stacking the second die and the third die to provide an overlap of a portion of the second die and a portion of the third die.

Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.