Abstract: An SOI semiconductor component having a portion of a circuit element in the handle wafer and a method for manufacturing the SOI semiconductor component. An SOI substrate has a handle wafer bonded to an active wafer via a dielectric material. A shallow trench isolation structure is formed from the active wafer. A plate or electrode of a capacitor is manufactured in the handle wafer. The other plate or electrode of the capacitor is formed through the shallow trench isolation structure. A circuit element is manufactured in the active wafer such that the manufacturing steps for forming the capacitor and those for forming the circuit element may be decoupled from each other.

Abstract: An underfill material for attaching and underfilling a semiconductor component on a substrate includes a polymer base material, and electrically conductive particles in the polymer base material. The particles are configured to melt and rigidify bonded electrical connections between solder terminal contacts on the component and substrate contacts on the substrate. A size and concentration of the particles is selected to prevent electrical conductivity in X and Y directions. A method for attaching and underfilling the component on the substrate includes the steps of depositing the underfill material on the substrate or the component, placing the terminal contacts in contact with the substrate contacts while the underfill material is in a viscous or B-stage condition, bonding the terminal contacts to the substrate contacts to form the connections, and then curing the underfill material to form an underfill layer.

Abstract: The present invention provides an integrated circuit, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 ?m, and a passive element formed directly or indirectly on the insulating region. It is desirable for the passive element to be an inductor.

Abstract: An electroplated metal alloy including at least three elements. A multilayer interconnection structure that includes a substrate that is an interior of the interconnection structure, a conductive seed layer exterior to the substrate, and an electroplated metal alloy layer including at least three elements exterior to the conductive seed layer. A multilayer interconnection structure formed on a substrate, that includes a barrier layer, and a conductive seed layer, wherein the improvement includes an electroplated metal alloy layer including at least three elements. A method for forming a multilayer interconnection structure that includes providing a substrate, depositing a conductive seed layer, and electroplating a metal alloy layer including at least three elements exterior to the conductive seed layer.

Abstract: A method of fabricating integrated circuit wafers, in accordance with this invention comprises the following steps. Provide an integrated circuit wafer having devices formed therein covered with a metal layer and a photoresist layer over the metal layer which is selectively exposed and developed forming a photoresist mask. Introduce the wafer into a multi-chamber system, patterning the metal layer by etching and then exposing the mask to light in a cooled chamber wherein the light is derived from a source selected from a mercury lamp and a laser filtered to remove red and infrared light therefrom before exposure of the wafer thereto. The chamber is cooled by a refrigerant selected from water and liquefied gas Then remove the wafer, and load it into a photoresist stripping tank to remove the photoresist mask with a wet photoresist stripper. Place the wafer in a batch type plasma chamber after removing the photoresist mask.

Abstract: A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.

Abstract: Disclosed is a method and an apparatus for manufacturing a barrier layer of semiconductor device. The disclosed comprises the steps of: forming an interlayer insulating layer having a contact hole on a semiconductor substrate; forming a Ti layer on the contact hole and on the interlayer insulating layer; and reacting the Ti layer with nitrogen radical to transform a part of the Ti layer into a TiN layer.

Abstract: An LCD fabricated by forming gate lines, gate electrodes, gate pads, vertical patterns, and a first gate shorting bar on a substrate, forming channels over the gate electrodes, forming data lines, source electrodes, drain electrodes, and a second shorting bar, forming a passivation layer, patterning the passivation layer to form drain contact holes to the drain electrodes, data pad contact holes to the data pads, first connecting contact holes to the first gate shorting bar, second connecting contact holes to the second gate shorting bar, and etching holes to the vertical patterns, forming a transparent conductive layer, and patterning the transparent conductive layer to form pixel electrodes, first pad connectors that connect odd numbered gate pads to the first gate shorting bar, and second pad connectors that connect the even numbered gate pads to the second gate shorting bar, wherein the vertical patterns are etched via the etching holes.

Abstract: An optoelectronic submount for providing optical connection and electrical connection to a vertically communicating optical device, such as a vertical cavity surface-emitting laser. The submount has a trench for holding the optoelectronic device on-edge, and electrical connection pits adjoining the trench. A metallization layer is disposed in the electrical connection pits. The electrical connection pits are aligned with the trench and optoelectronic device so that compact pads on the optoelectronic device can be soldered to the metallization layer. A groove can be provided in the submount for holding an optical fiber in alignment with an active area of the optoelectronic device.

Abstract: A new process flow is provided for the creation of a fuse contact and a bond pad. The invention starts with a semiconductor substrate over the surface of which is provided top level metal and fuse metal in the surface of a layer of insulation deposited over the surface of the substrate. A first etch stop layer is deposited over the surface of the layer of insulation over which a first passivation layer is deposited, an opening is created through these layers exposing the top level metal. A metal plug is created overlying the exposed surface of the top level metal. A stack of a patterned and etched hard mask layers, having been deposited at part of the creation of the metal plug and overlying a layer of metal plug material, remains in place over the surface of the created metal plug.

Abstract: The present invention provides a semiconductor device in which a V-groove for holding an optical fiber and an alignment groove for adjusting the distance between the optical fiber and an optical element chip are formed in an optical fiber packaging region on the upper face of a semiconductor substrate, and an optical element chip is packaged in an optical element packaging region on the upper face of the semiconductor substrate so that its optical axis matches the direction in which the V-groove extends. A semiconductor integrated circuit is formed on the lower face of the semiconductor substrate. Through holes are provided in the optical element packaging region of the semiconductor substrate, passing from its upper face to its lower face, and the optical element chip and the semiconductor integrated circuit are connected via the through holes.

Abstract: The invention relates to an apparatus and method for improving AC coupling between adjacent signal traces and between plane splits and signals spanning plane splits on circuit boards. A circuit board includes adjacent conductive means and an oxide means interposed there between. The oxide means is a copper oxide, e.g., cupric or cuprous oxide. In one embodiment, the adjacent conductive means are adjacent voltage reference planes with a split interposed between the conductive means. The copper oxide fills the split. In another embodiment, the adjacent conductive means are differential signal traces. The copper oxide fills a gap between the differential signal traces. The copper oxide is a non-conductive material with an increased dielectric constant as compared to other common dielectric materials used as fillers. The increased dielectric constant increases capacitance, in turn, increasing AC coupling.

Abstract: The invention includes a semiconductor construction comprising a semiconductor substrate, and a first layer comprising silicon and nitrogen over the substrate. A second layer comprising at least 50 weight % carbon is over and physically against the first layer, and a third layer consisting essentially of a photoresist system is over and physically against the second layer. The invention also includes methodology for forming the semiconductor construction.

Abstract: The method of the invention for producing a Group III nitride compound semiconductor, employing an etchable substrate which is produced from a material other than the Group III nitride compound semiconductor, includes stacking one or more layers of the Group III nitride compound semiconductor on one face of the substrate and etching the other face of the substrate while stacking one or more semiconductor layers or after completion of stacking one or more semiconductor layers, to thereby reduce the thickness of most of the substrate. The apparatus of present invention for producing a semiconductor through vapor phase growth, contains a substrate for vapor-phase-growing the semiconductor; a source-supplying system for supplying a source for vapor phase growth of the semiconductor; and an etchant-supplying system, wherein the source-supplying system and the etchant-supplying system are isolated through placement of the substrate.

Abstract: A semiconductor device is improved in adhesion between: at least a contact portion of its tantalum-base metal serving as a barrier metal film; and, its copper buried wiring brought into contact with the contact portion to prevent the copper buried wiring from peeling off, and is therefore improved in reliability. Formed in a trench designed for a buried wiring of an interlayer insulation film are: a tantalum film having a film thickness of from 200 to 500 angstroms; and, a copper buried wiring having a film thickness of from 1.1 to 1.55 ?m. This copper buried wiring is formed by stacking together a copper thin film having a film thickness of from 0.08 to 0.12 ?m and a copper thick film having a film thickness of from 1.0 to 1.5 ?m. Further formed between the tantalum film and the copper buried wiring is an amorphous metal film having a thickness of approximately angstroms.

Abstract: A high-voltage diode has a dopant concentration of an anode region and a cathode region optimized in terms of basic functions static blocking and conductivity. Dopant concentrations range from 1×1017 to 3×1018 dopant atoms per cm3 for the anode emitter, especially on its surface 1019 dopant atoms per cm3 or more for the cathode emitter and approximately 1016 dopant atoms per cm3 for the blocking function of an anode-side zone.

Abstract: A method and system for reducing wafer edge residue following a chemical mechanical polishing operation. A semiconductor wafer can be polished utilizing a chemical mechanical polishing apparatus. Thereafter, an acid etch operation may be performed to remove a residue, such as tungsten (W), collected on the semiconductor wafer as a result of the chemical mechanical polishing operation. A spin etch operation removes residue from the edges of the semiconductor wafer following chemical mechanical polishing of the semiconductor wafer.

Abstract: An apparatus for measuring ammonia gas concentration in an ongoing mechanical polishing (CMP) cycle utilizing an acidic CMP slurry, having the following components: a. A transferring means to collect a sample of the acidic CMP slurry; b. A converting means to convert the acidic CMP slurry to a basic slurry; c. A measuring means to measure the ammonia gas present in the basic slurry; d. A detection means to signal the end of an ongoing CMP cycle.

Abstract: The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor device. The resistor includes first and second crystalline layers which may or may not differ from one another. One of the first and second crystalline layers comprises doped silicon/germanium, and the other comprises doped silicon. The transistor device and resistor can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The invention also includes processes of forming semiconductor constructions, and in particular aspects, includes processes of forming resistor constructions.

Abstract: A conductive system and a method of forming an insulator for use in the conductive system is disclosed. The conductive system comprises a foamed polymer layer on a substrate. The foamed polymer layer has a surface that is hydrophobic, and a plurality of conductive structures are embedded in the foamed polymer layer. An insulator is formed by forming a polymer layer having a thickness on a substrate. The polymer layer is foamed to form a foamed polymer layer having a surface and a foamed polymer layer thickness, which is greater than the polymer layer thickness. The surface of the foamed polymer layer is treated to make the surface hydrophobic.