Abstract: In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

Abstract: A proxy device that may query other devices for their configurations is disclosed. The proxy device may include a device communication logic to communicate with the devices over a control plane. The proxy device may also include reception logic that may receive a query from a host. The query may request information from the proxy device about the configurations of the devices. The proxy device may also include a transmission logic to send the device configurations to the host.

Abstract: Systems and methods of a peripheral devices switching system configured to be connected to a plurality of host computers, including at least one set of peripheral devices, a peripheral devices switch that is to be coupled to said at least one set of peripheral devices and said plurality of host computers, where the peripheral devices switch assigns a color to each host computer, and couple between said at least one set of peripheral devices and an active host computer, and one or more polychromatic light sources that are being comprised in the peripheral devices switch, the at least one of the peripheral devices of the sets of peripheral devices or both, where the peripheral devices switch indicates the active host computer by illuminating at least one polychromatic light source by the color that is assigned to the active host computer.

Abstract: Data transfer devices as well as methods of interfacing, configuring, and using the same are disclosed. Data transfer devices described herein allow a proper communication interface to be mounted on an input device, e.g., a scanner, connected to the data transfer device, enabling communication between the input device and a host device. The data transfer devices allow the input device to be configured for communication with the host device based on a particular type of connection, e.g., a particular hardware attachment that utilizes a particular communication interface. The data transfer device therefore enables “plug-and-play” connectivity between an input device and a host device that removes the amount of user-configuration or user-modification that is required to establish a connection or have the input device, e.g., scanner, mount a proper interface that is compatible with the data transfer device.

Abstract: Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on each of the lanes.

Abstract: A computer-implemented method includes setting a respective flag in a first buffer of a hardware accelerator. The first buffer includes the respective flag of the first buffer, and a second buffer of the hardware accelerator includes a respective flag of the second buffer. A hardware state of the hardware accelerator is maintained in the first buffer, based on the respective flag of the first buffer being set. A first request directed to the hardware accelerator is received. It is determined that that the first buffer has the respective flag set. The first request is passed to the hardware accelerator, where passing the first request includes passing to the hardware accelerator a pointer to the first buffer, based on the first buffer having the respective flag set.

Abstract: Managing multiple cartridges that are electrically coupled together includes obtaining general purpose command instructions from a chassis with a cartridge where the cartridge has a unique application and is connected to the chassis and further operating the unique application based on the general purpose command instructions.

Abstract: A system and method for performing sleep state enhancements in a computing device using firmware and NVDIMMs that include DRAM and flash memory is discussed. The flash-backed DRAM covers all of platform memory. All writes to DRAM during system operation are propagated to the flash. Sleep state requests trigger a System Management Interrupt and a firmware a SMI handler handles the sleep state request so as to enable power savings during the sleep state and facilitate faster resume times when exiting the sleep state.

Abstract: A buffer (32) for temporarily storing a packet is installed in a packet order control circuit (12H). A comparison circuit (31) compares the packet ID of an input packet with a next-selection ID indicating the packet ID of a packet to be selected next in accordance with an order. If the comparison result indicates that the packet ID and the next-selection ID do not match, a control circuit (36) stores the input packet in a storage position corresponding to the packet ID. If the packet ID and the next-selection ID match, the control circuit (36) selects the input packet as a target of a transfer process without storing the packet in the buffer (32). If the next-selection ID matches the packet ID of a packet stored in the buffer (32), the control circuit (36) selects the packet as a target of the transfer process. This guarantees the packet processing order with few memory resources.

Abstract: Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.

Abstract: Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.

Abstract: Dynamic power dissipation in an integrated circuit device is related to switching activity and can degrade performance or cause premature failure. Methods and apparatuses for dynamic power reduction by limiting data transfer requests between execution engines and memory are provided. Data transfer limiter blocks can be associated with execution engines of the integrated circuit device. Each data transfer limiter block may include a set of counters to control a number of data transfer requests from an execution engine that are permitted to reach the memory in a specified period of time. The counters may incrementally increase the number of data transfer requests permitted to reach the memory subsystem from an initial number up to a maximum number of data transfer requests in the specified period of time.

Abstract: A router for routing signals on communications networks; said router comprising a plurality of I/O ports for input to the router of said signals and for output from the router of said signals; said router comprising at least one microprocessor; said router adapted such that said microprocessor communicates with at least one of said I/O ports independently of any Southbridge or platform controller hub (SPCH) associated with said microprocessor.

Abstract: A containerized storage microservice is described. The containerized storage microservice, and its corresponding architecture, provide an environment wherein an application container accesses containerized storage services through a direct connection. This allows the operating system file system to be effectively bypassed in the provision of storage services. In one example, a library provides a basic file system and is arranged underneath the application container. The library essentially intercepts storage requests and emulates a thin file system. Instead of invoking the kernel of the operating system to process each storage request, the library allows the storage request to bypass the kernel and pass the storage request to the storage microservice. The containerized storage microservices are available in different types, and are configured so that they can be stacked to provide customized sets of storage services to different types of application containers.

Abstract: In one embodiment, a computing device detects a module that is inserted into a first slot. The computing device includes a first slot to operate with a first type of module and a second slot to operate with a second type of module. The first slot and the second slot include a same pin position for receiving a power supply pin from the first type of module and the second type of module. The module is communicated with to determine whether the module is the first type of module or the second type of module. The first type of module receives a first type of signal that is combined with a second type of signal from the second type of module. The computing device adjusts a power supply voltage to the power supply pin of the first slot from a first value to a second value when the first type of module is detected.

Abstract: A method and system for manages mapping of universal serial bus (USB) connectors to a plurality of USB host controllers. The method determines an enumeration of USB connectors in a system, identifying USB host controllers in the system, generating a grouping for a USB connector with USB host controllers, and configures USB routing in the system to map the USB connector with the USB host controllers according to the grouping.

Abstract: An integrated circuit such as, for example a graphics processing unit (GPU), having an on-chip analog to digital converter (ADC) for use in overcurrent protection of the chip is described, where the overcurrent protection response times are substantially faster than techniques with external ADC. A system-on-chip (SoC) includes the integrated circuit and a multiplexer arranged externally to the chip having the ADC, where the multiplexer provides the ADC with a data stream of sampling information from a plurality of power sources. Methods for overcurrent protection using an on-chip ADC are also described.

Abstract: The electronic device includes a master element and a plurality of slave elements that are daisy-chain-connected. The slave element includes an input terminal connected to a slave element adjacently provided on the opposite side of the master element, an output terminal connected to the slave element adjacently provided on the side of the master element or the master element, and a first switch that is provided in a section between the input terminal and the output terminal used as a transmission path of transmission data and is connected to the transmission path in series. The master element receives the transmission data transmitted from the slave element to be the transmission source via the transmission path, and at least the slave element to be the transmission source includes a data transmission unit that is connected to the transmission path via a second switch and transmits the transmission data.

Abstract: An input/output (I/O) device for a distributed modular I/O system includes a base adapted to be connected to an associated support structure. A terminal block is connected to the base and includes a plurality of wiring connections adapted to be connected to field wiring of an associated controlled system. The I/O device further includes first and second I/O modules each including a plurality of removable single-channel I/O submodules that are each releasably connected to the base and each configured for a select I/O operation for input and output of data relative to the associated controlled system. One or more pairs of the single-channel I/O submodules can be configured to be redundant within or between the first and second I/O modules. Each of the single-channel I/O submodules is operatively connected to wiring connections of the terminal block through the base. The I/O device further includes first and second network switches connected to the base.

Abstract: In accordance with one aspect of the present description, a node of the distributed computing system has multiple communication paths to a data processing resource lock which controls access to shared resources, for example. In this manner, at least one redundant communication path is provided between a node and a data processing resource lock to facilitate reliable transmission of data processing resource lock signals between the node and the data processing resource lock. Other features and aspects may be realized, depending upon the particular application.