Abstract: Systems, methods, and apparatus for improving bus latency for trigger activation are described. One method includes using configuration information received from a serial bus and stored in a holding register to reconfigure a peripheral device in accordance with timing indicated by at least one edge in clock pulses transmitted on a clock line of the serial bus. A trigger is activated by detection of a first edge in the clock pulses. Bits of the holding register are transferred to a register that controls elements of the peripheral device when the trigger is actuated. The trigger may be activated as indicated by trigger activation information received in a datagram. The trigger may be activated as indicated by a start condition transmitted on the serial bus. The trigger may be enabled or disabled based on signaling state of a data line of the serial bus when the first edge is detected.

Abstract: Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a first processor configured to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device. The communication arrangement is configured to detect transfers from the first PCIe device to one or more addresses corresponding to an address range of the second PCIe device, and redirect the transfers to the second PCIe device without passing the transfers through a second processor that initiates the transfers.

Abstract: An electronic device comprises a clock request pad, a multiplexer and a control circuit. The clock request pad is arranged to refer to a first control signal to operate under a low voltage level or a high voltage level, to indicate whether the electronic device needs a clock signal generated from a clock generation circuit external to the electronic device. Said multiplexer is arranged to refer to a second control signal to output one of a voltage level of the clock request pad and a predetermined voltage level to function as a multiplexer output signal. The control circuit is coupled to said multiplexer, and refers to said multiplexer output signal to determine whether to control the electronic device to operate in a power-saving mode.

Abstract: In an assembly (2) for an airplane (4) with a line (12) and switching elements (14a,b) to connect the line (12) in a first operating mode (B1) to digital transceivers (16a,b) and in a second operating mode (B2) to an analog signal source/sink (18a,b) for the audio signal (A), the line (12) is operated in the first operating mode (B1) as a digital data bus for data (D) and in the second operating mode (B2) as an analog signal line for transmitting an analog audio signal (A) from the signal source (18a) to the signal sink (18b). In a corresponding method, the line (12) is operated in a first operating mode (B1) as a digital data bus for transmitting data (D) and the line (12) is switched to the second operating mode (B2) for transmitting the audio signal (A), and the audio signal (A) is transmitted from the signal source (18a) via the line (12) to the signal sink (18b).

Abstract: A new long-term memory erasing device, referred to as EasyClean, has been invented. In general, EasyClean is a stand-alone, dedicated function device which is designed for an untrained user, who is tasked with removing data from one or more long-term memory storage devices located in one or more computing devices (targets). EasyClean provides one or more target devices with bootable code. After a target is booted, EasyClean communicates with the target device and monitors the status of the data removal operation. EasyClean may communicate this status to the user. EasyClean may generate an Audit Trail and provide it to the user. EasyClean may accept input from a user, such as what type of data removal to perform. EasyClean may write data to a storage device after the data removal operation is complete.

Abstract: Embodiments of the present disclosure provide a burning apparatus and system. The burning apparatus includes: a processor, a wireless communication module, at least one peripheral interface, and a memory; the processor is electrically connected to the wireless communication module, the peripheral interface, and the memory, respectively; the memory is configured to store to-be-burned firmware and a system program required for operating the burning apparatus; the processor is configured to start the system program to control the wireless communication module to be wirelessly connected to a terminal device, and receive, through the wireless communication module, the to-be-burned firmware transmitted by the terminal device; and the processor is also configured to be electrically connected to at least one target board through the at least one peripheral interface, and write the to-be-burned firmware to the at least one target board through the at least one peripheral interface.

Abstract: Systems, methods, and apparatus for improving addressability of slave devices coupled to a serial bus are described. A method the slave device includes delaying transitions in a control signal received at an input pin of the slave device, enabling a counter after detecting a delayed first transition in the control signal, where the counter is configured to count pulses on a data line of a serial bus, transmitting a first pulse on the data line of the serial bus after enabling the counter, counting the first pulse and one or more additional pulses on the data line of the serial bus, and using an output of the counter to generate a unique identifier used for communicating over the serial bus. Each of a plurality of slave devices may be configured to transmit one of the additional pulses on the serial bus after the first transition occurs in the control signal.

Abstract: An extended storage device based on a PCIe bus is provided. The extended storage device includes: a video processing device and a RAID card. The video processing device is connected to the RAID card via a PCIe bus; and the RAID card is constructed by an embedded system on chip (SoC). The video processing device may be connected to the RAID card via the PCIe bus, and virtual hard disk nodes corresponding to respective physical hard disk nodes of the RAID card may be built at the video processing device, so that the video processing device may manage physical hard disk nodes of the RAID card as managing a local hard disk, and then may organize these virtual hard disk nodes into a virtual RAID node, while the complex RAID computing is actually achieved through the SOC of the RAID card without occupying resources of CPU of the video processing device, so that a normal operation of business of the video processing device can be ensured.

Abstract: A communication system includes a physical layer circuit, a link layer circuit, a transport layer circuit, and a memory circuit. The physical layer circuit is coupled to a first storage circuit. The link layer circuit is coupled to the physical layer circuit. The transport layer circuit is coupled to a second storage circuit. The memory circuit is coupled between the link layer circuit and the transport layer circuit. The memory circuit includes a memory. The memory is controlled to selectively transmit data in the second storage circuit to the first storage circuit, or transmit data in the first storage circuit to the second storage circuit.

Abstract: A USB (Universal Serial Bus) extension cord includes a connection cable, a male connector base, and a plurality of female connector housings. The male connector base is provided at one end of the connection cable, and the female connector housings are provided elsewhere on the connection cable at intervals. The male connector base is provided with a male USB connector, and each female connector housing is formed with at least one female USB connector. As each two adjacent female connector housings can be brought as far away from, and as close to, each other as the connection cable allows, the female connector housings can be easily arranged at appropriate positions in an environment to facilitate the use of low-voltage electricity.

Abstract: A memory system and an operating method thereof are disclosed. An operating method of a memory system including a nonvolatile memory device and a controller configured to control the nonvolatile memory device includes the controller updating original data of firmware stored in the nonvolatile memory device, the controller transmitting a notification signal, which notifies a host device of completion of the updating of the original data, to the host device when the updating of the original data is completed, and the controller updating backup data of the firmware stored in the nonvolatile memory device after the notification signal is transmitted.

Abstract: The present application relates to providing auxiliary port function distinction by illuminating a first light emitting diode around a data transfer capable port wherein the first light emitting diode is illuminated in a first color, illuminating a second light emitting diode around a charge only port, receiving a first data connection request at the charge only port, illuminating the first light emitting diode a second color in response to the data connection request, receiving a second data connection request at the data transfer capable port, initiating a data connection handshake between a device connected to the data transfer capable port and a processor in response to the second data connection request, and illuminating the first light emitting diode the second color in response to the initiation of the data connection handshake.

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.

Abstract: Circuitry of a physical layer for interfacing with a communication bus of a wired local area network is disclosed. The circuitry includes a variable delay driver operably coupled to a communication bus. The communication bus includes a shared transmission medium. The variable delay driver is configured to control a slew rate of a driven transmit signal at the driver output. The circuitry also includes receiver circuitry operably coupled to the communication bus. The circuitry further includes a common mode dimmer operably coupled to the receiver circuitry and the communication bus. The common mode dimmer is configured to protect the receiver circuitry from common mode interference.

Abstract: Methods and apparatus for boot time reduction in a processor and programmable logic device environment are disclosed. An example apparatus includes a multicore processor including a first core and a second core. A bootstrap processor is to initialize the first core into a standby mode and initialize the second core into a non-standby mode. A programmable logic device is to be programmed with instructions to be executed by the programmable logic device by the second core via a first connection initialized by the second core. The bootstrap processor is to, upon completion of the programming of the programmable logic device, initialize a data connection between the programmable logic device and the second core.

Abstract: A power management integrated circuit (PMIC) is described for providing system management bus (SMB) isolation, along with memory sub-systems which include such a PMIC and methods of operating such devices. In one embodiment, a PMIC comprises a voltage supply input, power management circuitry, and elements of a SMB. The SMB elements can include an SMB input, an SMB hot swap controller coupled to the SMB input, one or more SMBs, and one or more SMB outputs. When integrated with a memory sub-system, one SMB output can be connected to a memory controller and another SMB output to a microcontroller. During different power states (e.g., normal or low power states), certain outputs can be isolated in order to manage communications on the SMB during the different power states of the memory sub-system using the PMIC.

Abstract: Bootstrapping a programmable integrated circuit (IC) based network interface card (NIC) can include implementing, within the programmable IC, a first circuitry by loading a first stage configuration bitstream, wherein the first circuitry includes a bus endpoint configured to communicate with a host computer via a communication bus, a platform processor, and a first bootloader. The platform processor, executing the first bootloader, loads a first firmware within the programmable IC. A second circuitry is implemented within the programmable IC by the platform processor executing the first firmware to load a second stage configuration bitstream. The second circuitry includes a NIC controller. The platform processor, executing the first firmware, loads a second firmware within the programmable IC. The second firmware is executable to configure the second circuitry.

Abstract: A network adapter includes one or more network ports, multiple bus interfaces and a processor. The network ports are configured to communicate with a communication network. The bus interfaces are configured to communicate with multiple respective CPUs of a multi-CPU device. The processor is included in the network adapter and is configured to support an Option-ROM functionality, in which the network adapter holds Option-ROM program instructions that are loadable and executable by the multi-CPU device during a boot process, to expose the support of the Option-ROM functionality to the multi-CPU device over only a single bus interface, selected from among the multiple bus interfaces, and, by loading the Option-ROM program instructions to the multi-CPU device, to cause the multi-CPU device to present to a user only a single, non-redundant set of commands for managing all the multiple bus interfaces of the network adapter via the single bus interface.

Abstract: The present invention relates to a method for performing wake-up signalling between a host device and a client device of a communication system, said host and said client device being in a two-wire connection (1) with each other and at least one of said host and said client device being in an idle state, said host and said client device each comprising a data controller (3) arranged for data communication control and a power state controller (5) arranged to switch the device between at least an active state and said idle state, whereby the data controller of said at least one of said host and client device is disabled during the idle state.

Abstract: A method for controlling setup configuration is disclosed. The method for controlling setup configuration includes determining an alert standard format (ASF) corresponding to a plurality of setup configurations; and transmitting the ASF corresponding to the plurality of setup configurations to a client terminal, for enabling the client terminal to load the plurality of setup configurations of the ASF when rebooting.