Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.

Abstract: Circuitry of a physical layer for interfacing with a communication bus of a wired local area network is disclosed. The circuitry includes a variable delay driver operably coupled to a communication bus. The communication bus includes a shared transmission medium. The variable delay driver is configured to control a slew rate of a driven transmit signal at the driver output. The circuitry also includes receiver circuitry operably coupled to the communication bus. The circuitry further includes a common mode dimmer operably coupled to the receiver circuitry and the communication bus. The common mode dimmer is configured to protect the receiver circuitry from common mode interference.

Abstract: Methods and apparatus for boot time reduction in a processor and programmable logic device environment are disclosed. An example apparatus includes a multicore processor including a first core and a second core. A bootstrap processor is to initialize the first core into a standby mode and initialize the second core into a non-standby mode. A programmable logic device is to be programmed with instructions to be executed by the programmable logic device by the second core via a first connection initialized by the second core. The bootstrap processor is to, upon completion of the programming of the programmable logic device, initialize a data connection between the programmable logic device and the second core.

Abstract: A power management integrated circuit (PMIC) is described for providing system management bus (SMB) isolation, along with memory sub-systems which include such a PMIC and methods of operating such devices. In one embodiment, a PMIC comprises a voltage supply input, power management circuitry, and elements of a SMB. The SMB elements can include an SMB input, an SMB hot swap controller coupled to the SMB input, one or more SMBs, and one or more SMB outputs. When integrated with a memory sub-system, one SMB output can be connected to a memory controller and another SMB output to a microcontroller. During different power states (e.g., normal or low power states), certain outputs can be isolated in order to manage communications on the SMB during the different power states of the memory sub-system using the PMIC.

Abstract: Bootstrapping a programmable integrated circuit (IC) based network interface card (NIC) can include implementing, within the programmable IC, a first circuitry by loading a first stage configuration bitstream, wherein the first circuitry includes a bus endpoint configured to communicate with a host computer via a communication bus, a platform processor, and a first bootloader. The platform processor, executing the first bootloader, loads a first firmware within the programmable IC. A second circuitry is implemented within the programmable IC by the platform processor executing the first firmware to load a second stage configuration bitstream. The second circuitry includes a NIC controller. The platform processor, executing the first firmware, loads a second firmware within the programmable IC. The second firmware is executable to configure the second circuitry.

Abstract: A network adapter includes one or more network ports, multiple bus interfaces and a processor. The network ports are configured to communicate with a communication network. The bus interfaces are configured to communicate with multiple respective CPUs of a multi-CPU device. The processor is included in the network adapter and is configured to support an Option-ROM functionality, in which the network adapter holds Option-ROM program instructions that are loadable and executable by the multi-CPU device during a boot process, to expose the support of the Option-ROM functionality to the multi-CPU device over only a single bus interface, selected from among the multiple bus interfaces, and, by loading the Option-ROM program instructions to the multi-CPU device, to cause the multi-CPU device to present to a user only a single, non-redundant set of commands for managing all the multiple bus interfaces of the network adapter via the single bus interface.

Abstract: The present invention relates to a method for performing wake-up signalling between a host device and a client device of a communication system, said host and said client device being in a two-wire connection (1) with each other and at least one of said host and said client device being in an idle state, said host and said client device each comprising a data controller (3) arranged for data communication control and a power state controller (5) arranged to switch the device between at least an active state and said idle state, whereby the data controller of said at least one of said host and client device is disabled during the idle state.

Abstract: A method for controlling setup configuration is disclosed. The method for controlling setup configuration includes determining an alert standard format (ASF) corresponding to a plurality of setup configurations; and transmitting the ASF corresponding to the plurality of setup configurations to a client terminal, for enabling the client terminal to load the plurality of setup configurations of the ASF when rebooting.

Abstract: An on-vehicle system comprises a Clock Extension Peripheral Interface (CXPI) bus and a device coupled to the CXPI bus as a slave node. The device comprises a transceiver configured to: generate a first signal by delaying an inverted signal of a transmission data signal; generate a second signal based on the transmission data signal, where the second signal has a low slew rate; selectively output the first signal or the second signal as a third signal, in response to a selector signal; and generate a clock signal in response to the third signal, where the clock signal is at a high level when the third signal is at a low level, and where the clock signal is at the low level when the third signal is at the high level.

Abstract: In the event of a TDM failure, the associated computing device is either discarded or sent back to an original equipment manufacturer's facility for refurbishment. Field replacement of TDMs is typically not possible due to the lack of a secure process to recalibrate the touch controller to function properly with a replacement TDM. The presently disclosed systems and methods enable secure recalibration of a touch controller within a computing device to operate correctly with a new TDM field installed in the computing device. More specifically, the presently disclosed systems and methods provide a mechanism for detecting that a TDM has been field replaced, unlocking calibration data, performing a calibration process, and locking the new calibration data.

Abstract: A voltage regulator configuration system includes a voltage regulator module that is coupled to a processing system and that is configured to provide a voltage to the processing system. A Basic Input/Output System (BIOS) that is also coupled to the processing system and the BIOS identifies a processing system mode in which the processing system is operating and identifies a voltage regulator module configuration for the voltage regulator module based on the processing system mode. The BIOS transmits a voltage regulator module configuration command that includes the voltage regulator module configuration to a remote access controller. The remote access controller configures the voltage regulator module with the voltage regulator module configuration.

Abstract: A gateway processor of a vehicle includes a controller area network (CAN) message receiver, an Ethernet message receiver, a vehicle state monitoring and recognition unit configured to receive a signal from the CAN message receiver and the Ethernet message receiver, and a power management determination unit for each state configured to receive a signal from the vehicle state monitoring and recognition unit. The gateway processor also includes an electronic control unit (ECU) power control application execution unit configured to receive a signal from the power management determination unit for each state.

Abstract: In one embodiment, a link training controller is to train a link. The link training controller may be configured to: update a first link parameter of a link setting for the link to a first value; write data to the memory; read the data from the memory using the first value of the first link parameter; and in response to a determination that the data read from the memory does not match the data written to the memory, send an in-band link recovery command to the memory via the link to cause the memory to participate in a link recovery protocol with the apparatus. Other embodiments are described and claimed.

Abstract: A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A detector coupled to the first interface detects the OOB information. An encoder coupled to the detector encodes the OOB information into one or more symbols (e.g., control characters). A second interface is coupled to the encoder and a second communication link (e.g., a serial transport path). The second interface transmits the symbols on the second communication link. The device also includes mechanisms for preventing false presence detection of terminating devices.

Abstract: One embodiment provides for an electronic device comprising a first processor to execute a first operating system and a second processor to execute a second operating system. The second processor a set of input/output devices within the electronic device. The electronic device additionally includes an interconnect to enable communication between the first processor and the second processor. The operating systems include communication modules which establish a bi-directional network connection over the interconnect. Via the bi-directional network connection, the communication modules establish a multi-channel inter-process communication link between a first process on the first processor and a second process on the second processor to enable communication between the processes.

Abstract: An electronic control unit (ECU) is provided. The ECU is connected to a first network in an onboard network system. The onboard network system includes the first network and a second network. In the first network, first-type frames are transmitted following a first communication protocol. In the second network, second-type frames are transmitted following a second communication protocol. The ECU generates first-type frames following the first communication protocol, and transmits the generated first-type frames to the first network. The ECU receives external information indicating state information of a device on the onboard network system received from another electronic control unit connected to the first network or the second network, or receives external information indicating information received from a communication module configured to communicate with the server via an external network.

Abstract: Improvements to IEC 61968-9:2013 meter reading schemas. These include significantly compressing messages into a single integer number which, when transmitted over a utility's communication system, is used to configure meters at utility user locations, obtain meter data, command and control operations at a utility location, and expand messaging capabilities. A method is disclosed for simplifying the IEC 61968-9:2013 schema for communications between a HeadEnd utility communications facility and the meter at an EndPoint so to enable use of the schema for operations it could not previously perform. While providing this enhanced capability, the IEC 61968-9:2013 schema's ability to function for its intended purpose; i.e., meter reading and control, is not compromised or impeded.

Abstract: Methods, systems, and computer programs encoded on computer storage medium, for providing, by a client computing node, an interface identifying a secure boot certificate namespace hierarchy including a plurality of namespaces; in response to providing the interface, receiving, by the client computing node, a request to create a new namespace within the secure boot namespace hierarchy; configuring the new namespace, including adding a certificate that is to be included by the new namespace, the certificate associated with a server computing system; and assigning the new namespace to the server computing system.

Abstract: An input/output (I/O) level shifter for a subscriber identification module (SIM) interface includes a controller configured to apply a first enable signal to turn ON a first transmitter when the direction of packet flow is from an interface device to a SIM card, and is configured to apply a second enable signal to turn ON a second transmitter when the direction of packet flow is from the SIM card to the interface device. The controller is configured to not apply the first and the second enable signals concurrently. The controller selectively controls the ON/OFF period of the first and the second transmitter to maintain half-duplex communication on the interface I/O line and the SIM I/O line to prevent undesired positive data feedback.

Abstract: A memory system includes a plurality of memory dies and a controller coupled with the plurality of memory dies via a plurality of channels. The controller is configured to perform a correlation operation on at least some read requests among a plurality of read requests inputted from an external device so that the plurality of memory dies outputs plural pieces of data corresponding to the plurality of read requests via the plurality of channels in an interleaving way. The controller is configured to determine when to perform the correlation operation based on the number of the plurality of read requests.