Abstract: Software configuration deployment techniques for disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes instructing a communication fabric to establish a first partitioning in the communication fabric between a first processor and a storage element, and deploying at least a software configuration to the storage element using the first partitioning. The method includes instructing the communication fabric to de-establish the first partitioning, and instructing the communication fabric to establish a second partitioning in the communication fabric between a second processor and the storage element comprising the software configuration, wherein the second processor operates using the boot image.

Abstract: A multi-master hybrid bus apparatus is provided. The multi-master hybrid bus apparatus includes a hybrid bus bridge circuit configured to couple multiple master circuits with one or more slave circuits via heterogeneous communication buses. In examples discussed herein, the multiple master circuits can correspond to multiple physically separated master circuits or multiple bus ports provided in a single master circuit. In a non-limiting example, the hybrid bus bridge circuit is coupled to the multiple master circuits via multiple radio frequency front-end (RFFE) buses and to the slave circuits via at least one single-wire bus (SuBUS) consisting of a single wire. By bridging the multiple master circuits to the slave circuits based on a single hybrid bus bridge circuit, it may be possible to enable flexible heterogeneous bus deployment in an electronic device (e.g., a smartphone) with reduced cost and/or footprint.

Abstract: The invention relates to a PoE system, which comprises a powered device (2) and a power sourcing device (1). The power sourcing device comprises one or more ports (12) and the powered device is connectable to a port of the power sourcing device by an electrical conductor (13) for conveying the sourced power along with data. The powered device comprises an interface for providing a measure of its energy consumption within the PoE system and, if it does not have the ability to measure its energy consumption, is adapted to negotiate with the power sourcing device whether the power sourcing device has the ability to measure the energy consumption of the powered device and to provide the measured energy consumption to the powered device for provision via the interface. This can make the PoE system more flexible and allow for a single “point of contact” for providing energy usage feedback.

Abstract: Systems, methods, and apparatus for improving bus latency are described. Clock-cycle overhead associated with the transmission of trigger activation information may be reduced through the use of optimized datagram structures for register-configurable trigger activation mechanisms. A first mechanism defines a command code with a first Trigger-Activation datagram, and a second mechanism defines a command code with a second Trigger-Activation datagram that uses a 4-bit Magic-ID and eliminates 18 clock cycles from the conventional Extended Register Write datagram structure. A method performed at a device coupled to a serial bus includes generating a datagram that does not have an address field, populating a data payload of the datagram with trigger activation information directed to a plurality of slave devices coupled to a serial bus, and transmitting the datagram over the serial bus. Transmission of the datagram serves as a trigger that causes a configuration change in at least one slave device.

Abstract: Embodiments of the present disclosure provide a method, an apparatus and a computer program product for processing an Input/Output (I/O) request. In one embodiment, a method for processing an I/O request comprises: receiving, at a host, a first I/O request of a first type for a storage device, wherein at least a first path configured for processing I/O requests of the first type and a second path configured for processing I/O requests of a second type exist between the host and the storage device; selecting, from the first path and the second path, a path for processing the first I/O request; and processing the first I/O request via the path.

Abstract: A smart interface circuit includes: a first protocol processing circuit receiving several first protocol commands including a first command and a second command from a first device, storing the commands in an instruction register that is accessible to a second protocol processing circuit, and outputting first data and second data stored in a data buffer to the first device according to the first command and the second command respectively; and the second protocol processing circuit generating X second protocol command(s) according to the first command to request a second device to output the first data to the data buffer, and before the first protocol processing circuit finishes outputting the first data to the first device, the second protocol processing circuit generating Y second protocol command(s) according to the second command to request the second device to output the second data to the data buffer.

Abstract: A USB adapting circuit is suitable for being connected between a USB host and an external device. The USB adapting circuit includes a connecting port, a detecting circuit, a standby circuit and a main circuit. The standby circuit receives a power supply from the USB host and supplies the detecting circuit and the main circuit with the power supply. The detecting circuit is configured to output a connected signal when the external device is connected to the connecting port. The standby circuit outputs an enabling signal in response to the connected signal. The main circuit adapts between the USB host and the external device when receiving the enabling signal. Therefore, the main circuit does not work without receiving the enabling signal, and has a power saving effect.

Abstract: An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.

Abstract: Methods and apparatus for the safe negotiation of high current for a High-Definition Multimedia Interface (HDMI) active cable assembly. In one embodiment, a method for detecting a Power for Cable Assembly (PCA)-capable source is disclosed, the method including: detecting, by a cable assembly, an assertion of a defined voltage on a power supply pin; forwarding an assertion of a hot plug detect signal pin, by the cable assembly, from a sink device towards the PCA-capable source; detecting, by the cable assembly, a reduction in the defined voltage on the power supply pin for a defined period of time in response to the forwarding; and detecting, by the cable assembly, a re-assertion of the defined voltage on the power supply pin subsequent to the lapse of the defined period of time. PCA dependent cable assemblies and PCA capable source devices are also disclosed.

Abstract: A system includes a memory including a plurality of rings, an endpoint associated with a ring of the plurality of rings, and a gateway. The gateway is configured to receive a notification from the endpoint regarding a packet made available in the ring associated with the endpoint, access the ring with an RDMA read request, retrieve the packet made available in the ring, and forward the packet on an external network.

Abstract: A proxy device that may query other devices for their configurations is disclosed. The proxy device may include a device communication logic to communicate with the devices over a control plane. The proxy device may also include reception logic that may receive a query from a host. The query may request information from the proxy device about the configurations of the devices. The proxy device may also include a transmission logic to send the device configurations to the host.

Abstract: Disclosed is a system that enables connection of a wide variety of sensors to a smart device and, with the aid of a suitable software application or application processor, allows the sensor acquired information to be displayed on the smart device. Two basic embodiments of the system of the invention are described—an external unit that is connected to the smart device via one of the existing ports and an internal unit that in some cases utilizes some of the existing components of the device.

Abstract: Disclosed herein are techniques and a display panel that can sequentially display images while the host processor is inactive (e.g., asleep, power gated, or the like). The display panel includes circuitry to receive a set of encoded images, sequentially decode the encoded images provide a bitstream of the decoded images to the display electronics. The host is arranged to encode the images, send the encoded images to a frame buffer at the panel and configure the panel for a low power multi-image presentation mode.

Abstract: A computer system for performing control of an electronic control unit (ECU) having a processor for executing computer-readable instructions and a memory for maintaining the computer-executable instructions, the computer-executable instructions when executed by the processor perform the following functions by a processor. The functions include configuring a communication controller to while operating in a secure mode, transiting to an unsecure mode, executing a program in the unsecure mode that utilizes the communication controller; and in response to detecting a clock off request while a transmit buffer of the communication controller is not empty, inhibiting the clock off request until the transmit buffer is empty.

Abstract: A method for handling kernel services for interrupt routines in a multi-core processor in an electronic device. The method comprises receiving a first interrupt on a first core of the multi-core processor, wherein the first interrupt includes at least one kernel service request and at least one non-kernel service request. The method further determines whether a worker queue of the first core in empty and whether a kernel service lock for the at least one kernel service request is acquired by at least one second core of the multi-core processor, in response to determining that the worker queue of the first core is empty. The method further comprises executing the at least one non-kernel service request of the first interrupt on the first core. The pending kernel service request are queued in the worker queue based on whether worker queue is empty or not and availability of kernel lock.

Abstract: The present disclosure provides a Type-C interface controlling circuit, a controlling method, and a mobile terminal, wherein the Type-C interface controlling circuit includes: a Type-C interface, a first transmission module, a second transmission module, a switching module, and a detection module. The first end of the detection module is connected to the Type-C interface for detecting a connection state of the Type-C interface, and the second end of the detection module is connected to the switching module, and the detection module controls a connection relationship between the first end of the switching module and the second end of the switching module according to the connection state.

Abstract: Embodiments of the present invention relate to a control system and a control method for controlling memory modules. In the embodiments, the control system includes a central processing unit (CPU) and a plurality of memory modules, each of which includes a display unit and a micro control unit (MCU) configured to control the display unit. The CPU and the MCUs are connected through a bus, and the CPU instructs, according to a preset bus address, the MCUs to synchronously control the respective display units.

Abstract: Examples may include chipsets, processor circuits, and a system including chipsets and processor circuits. The chipsets and processor circuits can be coupled together via side band interconnect. The chipsets and processor circuits can be coupled together dynamically, during runtime using the side band interconnects. A chipset can send control signals for other chipsets and/or receive control signals from processor circuits via the side band links to dynamically coordinate the chipsets and processor circuits into systems.

Abstract: The present invention relates to a computer-implemented method for replacing a data string by a placeholder in a replacement device and, when necessary, for reconstituting the data string from the placeholder in the replacement device. There is a need for a central system for replacing a data string by a placeholder for a whole company which enables all applications to be protected and, when necessary, to have controlled access to sensitive data strings. It is necessary to make possible a central administration but at the same time to offer application-related access points throughout the company without long network communication paths.

Abstract: A method of operating a computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. Each of rack modules can include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.