Abstract: A management device that may communicate with at least one devices is disclosed. The management device may include a communication logic to communicate with the devices over a communication channels about data associated with the devices. The management device may also include reception logic that may receive a query from a host. The query may request information from the management device about the devices. The management device may also include a transmission logic to send the data about the devices to the host. The host may be configured to send a message to the devices.

Abstract: A method of downloading a firmware to a server is disclosed as including providing a server with a mainboard with a baseboard management controller (BMC) and at least one universal serial bus (USB) port, connecting the USB port to a USB device controller of the BMC of the server, resetting the BMC, connecting a data processing device with the server via the USB port, and downloading a firmware to the BMC from or through the data processing device via the USB port.

Abstract: According to one embodiment, a transceiver includes a sampler, a pipeline, and a transmission circuit. The sampler takes a data signal received from a host at a timing based on a data strobe signal received from the host. The pipeline transfers the data signal taken by the sampler using at least a clock signal, different from the data strobe signal, as a drive signal. The transmission circuit acquires and transmits a data signal having passed through the pipeline.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transition devices between operational modes. An example apparatus comprising: an activity detector configured to be coupled to a communication bus; a communication bus controller coupled to the activity detector; a hardware wakeup controller coupled to the activity detector; a switching circuit coupled to the hardware wakeup controller; a first oscillator coupled to the switching circuit; and a second oscillator the second oscillator coupled to the switching circuit and the hardware wakeup controller.

Abstract: Systems, methods, and apparatus for power management are disclosed. A power management integrated circuit has a bus interface circuit configured to couple the power management integrated circuit to a shared communication bus, one or more regulator circuits configured to provide current to a managed device, and a controller. The controller is configured to determine that current consumption by the managed device exceeds a threshold level, generate an extended current level message to be transmitted over the shared communication bus to the managed device and transmit a time value with the extended current level message, the time value indicative of an elapsed time between generation of the extended current level message and start of transmission of the extended current level message.

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

Abstract: A management device that may communicate with at least one devices is disclosed. The management device may include a communication logic to communicate with the devices over a communication channels about data associated with the devices. The management device may also include reception logic that may receive a query from a host. The query may request information from the management device about the devices. The management device may also include a transmission logic to send the data about the devices to the host. The host may be configured to send a message to the devices.

Abstract: Systems, methods, and apparatus are configured to enable a receiver to provide feedback. A feedback mechanism enables a transmitting device to identify the provider of feedback for a multicast transmission, and the feedback transmitted by one or more individual receivers of the multicast transmission. A method includes receiving a multicast write command from the serial bus in a first datagram, writing a data byte received in a first data frame of the first datagram to a register address identified by the first datagram, and providing device-specific feedback regarding the first datagram in a multibit slot within the second data frame. The multibit slot is one of a plurality of sequential multibit slots defined for the second data frame. Each multibit slot in the plurality of sequential multibit slots may provide device-specific feedback from one receiving device addressed by the multicast write command.

Abstract: A method of creating a new page table structure after first stage boot operations has completed but before handoff to a hypervisor occurs. Firmware page tables are reused and copied to a region of memory by a first-stage bootloader while the firmware is running, processed to have an expected multi-stage page table structure and desired access rights, and copied again to another region of memory by the first-stage bootloader after the first-stage bootloader has completed its booting operations and after the firmware has been quiesced.

Abstract: An information handling system may include an embedded controller, a serial peripheral interface (SPI) read-only memory (ROM) device to store a first basic input/output system (BIOS) firmware for the information handling system, and a non-volatile memory device includes a boot partition to store a second BIOS firmware. The embedded controller detects a failure during a boot process, switches a first SPI of a chipset from the SPI ROM to the embedded controller and executes the second BIOS firmware from the non-volatile memory device via a sideband access of the non-volatile memory device.

Abstract: A peripheral devices switch, a peripheral device, and a keyboard configured to be connected to a plurality of host computers. The peripheral devices switch configured to be coupled to at least one set of peripheral devices and to a plurality of host computers. A color is assigned to each host computer and the at least one set of peripheral devices illuminates at least one polychromatic light source with the color that is assigned to an active host computer. A peripheral device interface to interface between the peripheral device and the peripheral devices switch may be a composite interface comprises two independent interface protocols either by sharing a single connector and cable but having separate pins in the connector and corresponding wires in the cable, or by having a separate cable and separate connector to each one of said interface protocol.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an interface having a first bi-directional channel and a second bi-directional channel. The interface operates in one of a first operational state and a second operational state, and performs an exemplary power-saving scheme if it is operating in the second operational state. The interface may detect a plurality of power states and initiate the power-saving scheme based on the detected power state. The plurality of power states may comprise a first power state (low current mode), a second power state (high current mode), and a third power state (mid-current mode).

Abstract: Systems and methods for staggering the release of multiple endpoints from a power brake event. A MCU on each riser implements a riser offset delay based on its position in an order in which power is to be released. For a riser with multiple slots, a delay circuit may be connected to one or more slots to provide a unique offset time to delay the release of power supply the slot. In some systems, a baseboard management controller (BMC) identifies endpoints subject to a power brake event during a POST process. Risers and slots that are not subject to a power brake event are identified and not included in the determination of delays or offset times.

Abstract: There is disclosed in one example a multi-core computing system configured to provide a hot-swappable CPU0, including: a first CPU in a first CPU socket and a second CPU in a second CPU socket; a switch including a first media interface to the first CPU socket and a second media interface to the second CPU socket; and one or more mediums including non-transitory instructions to detect a hot swap event of the first CPU, designate the second CPU as CPU0, determine that a new CPU has replaced the first CPU, operate the switch to communicatively couple the new CPU to a backup initialization code store via the first media interface, initialize the new CPU, and designate the new CPU as CPUN, wherein N?0.

Abstract: Methods, apparatus, and systems for clock and data recovery in a C-PHY interface are disclosed. A receiving device has a plurality of differential receivers and a recovery circuit. The differential receivers are configured to generate difference signals. Each difference signal is representative of voltage difference between one pair of wires in a three-wire serial bus. The recovery circuit is configured to identify a first difference signal that has the greatest voltage magnitude among the plurality of difference signals in a first unit interval and determine signaling state of the three-wire serial bus for the first unit interval based on identity of the pair of wires corresponding to the first difference signal and polarity of the first difference signal in the first unit interval, and to generate a first edge in a clock signal responsive to a transition in the first difference signal during the first unit interval.

Abstract: Methods and apparatus for implementing a bus in a resource constrained system. In embodiments, a first FPGA is to a parallel bus and a second FPGA is connected to the first FPGA via a serial interface but not the parallel bus. The first FPGA processes a transaction request, which has a parallel bus protocol format, to the second FPGA by an initiator and converts the transaction request to the second FPGA into a transaction on the serial interface between the first and second FPGAs. The first FPGA responds to the initiator via the parallel bus indicating that the transaction request in the format for the parallel bus to the second FPGA is complete.

Abstract: A non-volatile memory express (NVMe) based storage system may include a processor; an input/output (I/O) port operatively coupled to a data network; a drive interface board (DIB), including: a PCIe switch communicatively coupled to the processor to receive signals from the processor to a plurality of NVMe storage devices; and a source clock communicatively coupled to the PCIe switch; a connector communicatively coupling the DIB to relay clock signals to a plurality of NVMe drives at a drive mid-plane baseboard; the drive mid-plane baseboard communicatively coupled to the source clock, the drive mid-plane baseboard including: a clock distribution module to receive a source clock signal from the source clock, the clock distribution modules placed at the drive baseboard to distribute the clock signals to the plurality of NVMe storage devices.

Abstract: A memory card includes a first ground terminal arranged in a first row that provides a ground voltage to at least one nonvolatile memory or a memory controller, universal flash storage (UFS) terminals arranged in a second row including a first UFS terminal that provides a second power, a second UFS terminal that provides a reference clock signal, and a third UFS terminal that provides a path for input/output data to the memory controller, and a first power terminal arranged in a third row that provides a first power supply voltage (VCC) to the at least one nonvolatile memory or the memory controller. The memory card has a size defined by a nano subscriber identification module (SIM) card standard, the first ground terminal corresponds to a “C5” terminal of the nano SIM card standard, and the first power terminal corresponds to a “C1” terminal of the nano SIM card standard.

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

Abstract: This application discloses a power consumption control method and system for an electronic positioning device, and an electronic positioning device. The method includes: obtaining sensing data of a sensor for sensing a physical quantity of an object's state of motion (101); determining, based on the sensing data, whether a current condition meets a preset trigger condition, to obtain a first determining result (102); sending a first control instruction when the first determining result indicates that the current condition meets the preset trigger condition (103), where the first control instruction is used to enable a positioning module in the electronic positioning device such that the positioning module is in an on state; and maintaining the positioning module in an off state when the first determining result indicates that the current condition does not meet the preset trigger condition (104).