Abstract: Presented herein are embodiments for providing and using a symbolic name for referencing an element of a non-volatile memory express (NVMe™) entity in an NVMe™-over-Fabric (NVMe-oF™) environment. In one or more embodiments, the symbolic name may be used to identify an element of an NVMe™ host or NVM subsystem in one or more processes. In one or more embodiments, a symbolic name may be provided as part of a registration process. Symbolic names may be used for identifying elements when performing other processes, such as masking and zoning for granting access rights. In one or more embodiments, a symbolic name may be shared by two or more elements.

Abstract: An apparatus including a host system is provided. The apparatus includes a peripheral device in communication with the host system. The apparatus also includes a programmable memory unit within the peripheral device. The programmable memory unit is to receive a configuration profile from the host system. The configuration profile is to re-configure as an embedded device. In addition, the apparatus includes a power delivery system to provide power to the programmable memory unit and to provide power to an accessory of the peripheral device separately. The power delivery system provides power to the programmable memory unit to allow re-configuration of the peripheral device as the embedded device.

Abstract: A bridge chip with a function of expanding external devices and an associated expansion method are provided, wherein the bridge chip may include at least one transmission interface, a bridge control unit and a connecting port. The transmission interface may be configured to make at least one external device outside the bridge chip couple to the bridge chip; the bridge control unit is coupled to the transmission interface, and may be configured to control priority of the external device for performing data transmission; and the connecting port is coupled to the bridge control unit, and may be configured to make the bridge chip couple to a host device, to allow the host device to perform data transmission with the external device. More particularly, a number of the external device is expandable.

Abstract: An embodiment method comprises receiving at least one frame comprising consecutive bits transported by a serial bus; estimating an arrival period of a last bit of the consecutive bits; and starting a sending of an acknowledgement of receipt before the end of the estimated arrival period.

Abstract: An information handling system includes a basic input/output system (BIOS) that performs a firmware boot operation. During the firmware boot operation, the BIOS determines whether a driver pack management controller setting is enabled within a baseboard management controller of the information handling system. In response to the driver pack management controller setting being enabled, the BIOS copies a binary utility from the baseboard management controller to a system memory, and creates an operating system specific platform binary table to point to the binary utility on the baseboard management controller. In response to the operating system being initialized, a processor invokes the binary utility, mounts a memory partition of the baseboard management controller as a virtual drive of the operating system, and executes the operating system specific binary stage under a fixed globally unique identifier to install a driver pack.

Abstract: A memory system for storing and retrieving data may include a controller, a first switch, a second switch connected to the first switch via an interconnecting bus, and a plurality of memory devices. The controller may have a first serial interface. The first switch may have one or more serial interfaces and one or more memory ports. The first serial interface of the controller may be communicatively connected to a first serial interface of the one or more serial interfaces of the first switch via a first serial bus. Each of the one or more memory ports of the first switch may be communicatively connected to a subset of the plurality of memory devices via a memory bus. The first switch may transfer data between the controller and the subsets of the plurality of memory devices via the one or more memory ports.

Abstract: An input/output (I/O) device for a distributed modular I/O system includes a base adapted to be connected to an associated support structure. A terminal block is connected to the base and includes a plurality of wiring connections adapted to be connected to field wiring of an associated controlled system. The I/O device further includes first and second I/O modules each including a plurality of removable single-channel I/O submodules that are each releasably connected to the base and each configured for a select I/O operation for input and output of data relative to the associated controlled system. One or more pairs of the single-channel I/O submodules can be configured to be redundant within or between the first and second I/O modules. Each of the single-channel I/O submodules is operatively connected to wiring connections of the terminal block through the base. The I/O device further includes first and second network switches connected to the base.

Abstract: An information handling system includes a system board configured to serialize sideband signals from a sideband cable resulting in serialized sideband signals, and a peripheral device expansion card that has a power management embedded controller. If the sideband cable is connected to the peripheral device expansion card, then the controller may transmit the sideband signals to a card controller. If the sideband cable is not connected to the peripheral device expansion card, then the controller may decode and parallelize the serialized sideband signals resulting in parallelized sideband signals, and transmit the parallelized sideband signals to the controller. The controller determines a power state of the information handling system based on the sideband signals from the sideband cable or the parallelized sideband signals.

Abstract: Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.

Abstract: Presented herein are embodiments for implicitly or indirectly registering elements of a non-volatile memory express (NVMe™) entity in an NVMe-over-Fabric (NVMe-oF) environment. In one or more embodiments, one or more interactions between an NVMe™ entity and a centralized storage fabric service component, such as part of the Link Layer Discovery Protocol (LLDP) process or the Multicast Domain Name System (mDNS) process, may be used by the centralized storage fabric service to extract information about the NVMe™ entity and automatically register it with a centralized registration datastore. In one or more embodiments, the centralized registration datastore may be used to facilitate services in the NVMe-oF system, such as discovery of NVMe™ entities, provisioning, and access control. In one or more embodiments, an implicitly registered NVMe™ entity may also subsequently explicitly register, which may include supplying additional information about the NVMe™ entity.

Abstract: Presented herein are systems and methods for facilitating access control among elements of a non-volatile memory express (NVMe™) entity in an NVMe™-over-Fabric (NVMe-oF) environment. In one or more embodiments, NVMe™ entities, whether NVMe™ hosts or NVMe™ subsystems, can obtain information about elements of NVMe™ entities that have registered with a centralized storage fabric service component via a discovery controller of the centralize service. In one or more embodiments, based upon information received from requesting NVMe™ entities, the centralized storage fabric service creates and maintains a data store of zones, in which a zone comprises a listing of elements of NVMe™ entities that are members of that zone and have access rights relative to other members of that zone.

Abstract: An information handling system may include a host system having an initial operating system image deployed thereon; and a management controller configured to provide out-of-band management of the information handling system. The management controller may be further configured to: receive, via a secure management network, a request to configure a plurality of operating system settings; transmit, to an initial agent executing on the operating system, one or more instructions to configure the plurality of operating system settings in accordance with the request; and after the configuration of the plurality of operating system settings, allow a user to log in to the operating system via a non-secure data network.

Abstract: Disclosed is a home bus system (HBS) circuit, applicable to home bus (HB) communication implemented using a Microchip chip. The circuit includes the Microchip chip, an HBS communication chip, a resistor, a capacitor, and a transistor, the Microchip chip includes a universal asynchronous receiver/transmitter (UART) input pin and a serial peripheral interface (SPI) output pin, and the HBS communication chip includes an input pin. The transistor has a base coupled to the SPI output pin and a first end of the capacitor, a collector coupled to a first end of the resistor and the input pin of the HBS communication chip, and an emitter grounded, wherein a second end of the resistor is coupled to a power supply, and a second end of the capacitor is grounded.

Abstract: An interrupt system for RISC-V architecture includes an original register in a CLIC, a pushmcause register, a pushmepc register, an interrupt response register, and an mtvt2 register; the pushmcause register is used to store a value in an mcause on a stack by means of an instruction; the pushmepc register is used to store a value in an mepc on a stack by means of an instruction; the interrupt response register is used to respond to a non-vectored interrupt request issued by a CLIC by means of an instruction, obtain an interrupt subroutine entry address, and modify a global interrupt enable; and the mtvt2 register is used to store a base address of an non-vectored interrupt in a CLIC mode.

Abstract: A multi-die and multi-core computing platform in which multiple dies share the same storage device for firmware code storage is shown. After a slave die loads #1 firmware code from the storage device through a bus, the right to use the bus is released by the slave die and the slave die outputs a #0 enable signal to a master die. According to the #0 enable signal, the master die gains the right to use the bus. Through the bus, the master die loads #0 firmware code from the storage device. The slave die executes the #1 firmware code and the master die executes the #0 firmware code to initialize a link between the master and slave dies.

Abstract: A single communication interface between a master device and at least one slave device and a method with internal/external addressing mode using the single communication interface. In the single communication interface between a master device and at least one slave device, the master device includes a master interface and the slave device comprises a slave interface and a slave bus-system, whereas the slave interface is directly connected to the slave bus-system, wherein the master interface and the slave interface communicate on a packet based protocol by an internal and external addressing mode inside the slave interface, whereas the addressing mode, data transfer direction and data address location are coded by the packet based protocol inside a first 32-bit word of each transmission between the master device and slave device over the single communication interface.

Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

Abstract: This disclosure generally relates to USB TYPE-C, and, in particular, DISPLAYPORT Alternate Mode communication in a USB TYPE-C environment. In one embodiment, a device determines a DISPLAYPORT mode and determines an orientation of a USB TYPE-C connector plug. A multiplexer multiplexes a DISPLAYPORT transmission based in part on the determined orientation of the USB TYPE-C connector plug.

Abstract: An electronic control unit (ECU) includes a processor, a Controller Area Network (CAN) controller, clock gating logic, and security gating logic. The CAN controller having a status and configured to receive data and control signals from the processor, and a clock signal, package the data to create a CAN protocol frame held in at least one transmit buffer, and shift the CAN protocol frame to a CAN transceiver that is configured to transmit the CAN protocol frame to a CAN bus. The clock gating logic may be configured to selectively disable a clock signal to the CAN controller based on a control signal from the processor. The security gating logic configured to, in response to the status of the CAN controller being active, inhibit disabling the clock signal.

Abstract: A host device is configured to communicate over a network with a storage system. The host device comprises a multi-path input-output (MPIO) driver configured to control delivery of input-output (IO) operations from the host device to the storage system over selected ones of a plurality of paths through the network. The MPIO driver is further configured to create a disk device on the host device, wherein the disk device corresponds to a subset of the plurality of paths to the storage system, and to execute a script enabling a boot image create operation to run on the created disk device.