Abstract: A system for preventing permanent loss of work product from a volatile memory (30) of an information processing device (12) when such work is temporarily lost, erased, or corrupted owing to power failure, equipment malfunction, operator error, or other misadventure. When the information processing device (12) is turned on, the system is automatically loaded from a non-volatile memory (44) into a volatile memory (14) where it then resides (block 32). The system thereafter causes every substantive input (including data, positional information, and data formatting and manipulating instructions, but not ancillary inputs such as a view directory or print command) to the information processing device (12) to be stored immediately, and essentially quantum by quantum, in the non-volatile memory (44) concurrently with its initial processing in the volatile memory (14). When work is lost from the volatile memory (14), the system reconstructs it either automatically or semi-automatically, as selected by the operator.

Abstract: A performance diagnosis system (PDS) is utilized to analyze, diagnose and provide reports concerning the operation of a computer system. The PDS includes a system model database that contains historical and configuration information which is received on a periodic basis from resource managers within the computer system. The information is updated on a regular basis by individual collectors which are coupled to the resource managers. A reporter receives the historical and configuration information from the database to provide reports on different aspects of the performance of the computer system. In addition, different types of assessments of performance of the computer system is provided by the PDS.

Abstract: In a switching system, a data bus is provided for interconnecting circuit modules, a switching network module and a control module for transporting packets between the interconnected modules. A bus interface (16) is connected to the data bus (13) for receiving a copy of every packet on the data bus. An error detector (18) determines whether the received packet contains an error, and produces an error detect signal and an error check result if the received packet is determined as having an error. In response to the error detect signal, the received packet, the error check result and time-of-day data are stored into a register (19) and transferred to one of the storage locations of a memory (20) to keep a list of error records. A maintenance station (22) reads stored error records from the memory for identifying the source of errors.

Abstract: A circuit for resetting a system controller includes a level detector and a watch-dog circuit. The level detector compares a first reference voltage with a supply voltage provided to the system, and provides output of a first reset signal indicating that the controller is in an abnormal state in dependence upon the comparison between the first reference voltage and the supply voltage. The watch-dog circuit compares a second reference voltage with a voltage exhibited by the first reset signal, and provides output of a second reset signal to the controller to reset the controller in dependence upon the comparison between the second reference voltage and the voltage exhibited by the first reset signal. A connector provides the first reset signal from the level detector to the watch-dog circuit.

Abstract: An apparatus for disabling a watchdog function of a watchdog circuit when a watchdog input pin of the watchdog circuit fails to receive an externally pulsed signal, which has a first predefined period. The watchdog circuit, while the watchdog function is enabled, generates a watchdog fault condition if the externally pulsed signal is not received at the watchdog input pin by the end of a predefined watchdog timeout period. The apparatus includes a pulse generation circuit for generating a pulsed signal having a second predefined period, the second predefined period being shorter than the watchdog timeout period. Further, the apparatus includes a drive circuit coupled to the pulse generation circuit and the watchdog input pin. The drive circuit provides an internally pulsed signal to the watchdog input pin at a predefined current level, responsive to the pulsed signal from the pulse generation circuit.

Abstract: A multi-component system for linking a user to a product or service provider includes a user processing device, a storage device, and a provider device. The storage device stores provider-specific application software, user-specific data, and a file management program. The storage device and the processing device are coupled to each other to form a user device which communicates with the provider device. Under direction of the file management program, the processing device carries out a recognition methodology which determines whether the processing device and the storage device are authorized to operate with each other. This aspect of the system makes it possible to render the storage device operable only with a specific user processing device, referred to as the principal processing device. This, in turn, reduces the possibility of fraud since the storage device cannot be used without the principal processing device.

Abstract: A data processing system using a storage management server provides a method and apparatus for preserving consistency between a database back-up and a set of storage volumes. The system includes a plurality of client systems coupled to the storage management server. Primary and back-up copies of client files are stored within a set of attached storage volumes. The server contains a server database to maintain directory and reference location information linking the primary and back-up copies of the client files. The server periodically performs an incremental back-up of the server database to a database back-up. The server utilizes a reuse delay criterion to set selected storage volumes as pending volumes. Pending volumes are not eligible for reuse by the server, thereby preventing the server from overwriting these pending volumes and invalidating reference location information for the pending volumes stored in the database back-up.

Abstract: A method and a device for determining that digital information written into a memory is correctly readable before such read information, in the form of a number of coordinated bit positions, is used to control one or several functions, where the functions can be activated by a computer unit. A selected address position or positions within the memory corresponding to the stored digital information points out a first set of bits, required to control and/or initiate the functions, and a second set of bits serving as a control sum. The second set of bits is calculated taking into consideration the current set of bits corresponding to the first set of bits and a third set of bits, corresponding to the address position currently selected for readout.

Abstract: A method for protecting information bits wherein input data bits, at least some of which are to be protected, are sorted based upon information determined from a subset of the input data bits. An error control coding technique is applied to at least some of the sorted bits. In the preferred embodiment, an input data stream of voice coder bits is separated into arrays of bits. A first array (302) comprises voice coder bits needing error protection, with the bits arranged in order of importance determined by voicing mode. The second array (303) comprises bits that will not be error protected. The bits from the first array are provided to the input of an encoder (304), then the encoded bits are combined (305) with the bits from the second array (303) to form a bit stream.

Abstract: A system and method for automatically assigning addresses to agents on a system management bus in a computer system without requiring user intervention, i.e., without requiring the user to manually or programmatically set physical or logical switches. The computer system includes a system management bus which preferably uses the I.sup.2 C serial protocol. The bus includes at least one SMB master and a plurality of slaves for performing desired monitoring and control functions in the computer system. According to the present invention, the SMB master assigns unique addresses to each of the SMB slaves automatically and without user intervention. This provides a simpler, more efficient, and less error prone method for assigning addresses to SMB agents. In addition, the system of the present invention automatically assigns unique addresses to new devices inserted on the bus while the bus is operating and thus allows for hot pluggable devices.

Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.

Abstract: In order to perform a predetermined function, to detect failures, and to further perform the function after detection of a failure, a computer comprises two redundant processing chains and a monitoring device monitoring operating of the two chains, each chain comprising an acquisition circuit, a transmission circuit, and a processor performing the function and monitoring operating of the acquisition and transmission circuits of the other chain, and of the monitoring device, and issuing operating statuses of the elements monitored, the computer further comprising a voting device receiving the operating statuses in order to determine which elements have actually broken down, and a selection device intended to only output from the computer the results provided by a chain operating properly.

Abstract: A method and apparatus by which the partial error check value for all preceding data in a sector is updated each time a new data item is written into a data buffer during a transfer from a host computer to a system storage device. The partial check value is written into the buffer location following the location containing the most recently buffered data item from the associated sector. Thus, after the entire sector has been transferred into the buffer, the final check value for that sector will be available in the buffer location following the location containing the last written data from the associated sector. Upon readback of a sector from the storage device, the sector size is longer by one data item since the appended check value is treated as the last data item of the sector. When the sector is read back from the storage device, the check value is again updated with the entry of each data item.

Abstract: A hot spare boot circuit that automatically switches from a non-operational CPU to an operational CPU for powering up the computer system. In the multiprocessor computer system, a first CPU is designated to perform power on operations. If the first CPU fails, which is determined when a dead man counter in the hot spare boot circuit times out, the hot spare circuit ensures that the first CPU is in a disabled state. Next, the hot spare boot circuit identifies an operational second CPU, reinitializing certain ID information as necessary such that the second CPU can properly perform power on operations. The hot spare boot then awakens the second CPU, using a startup interprocessor interrupt in one embodiment, or simply negating the hard reset of the second CPU in a second embodiment. The second CPU then proceeds to perform the power on functions.

Abstract: An apparatus may be used with a computer system having a PCMCIA interface. The apparatus employs a DRAM device and logic for converting the PCMCIA SRAM control signals into DRAM control signals, so as to permit the communication of data and control signals between the computer system and the DRAM device. The apparatus further provides controls for refreshing the DRAM device, and for arbitrating between the functions of refreshing the DRAM and providing for communication between the DRAM and the computer system. The apparatus further provides the power management functions required for operating a DRAM device in a PCMCIA environment.

Abstract: A method is described for rapidly recovering a multi-processor data processing system from failure of a boot disk. Each data processing unit in the system has a private boot disk, and at least one shared disk. The processing units are interconnected so that each processing unit has access to its own private boot disk and also to the shared disks in all of the processing units. If the boot disk of one of the processing units fails, the system is temporarily reconfigured to connect a new boot disk in place of the shared disk in that processing unit. Another of the processing units is then operated to copy the contents of its own boot disk to the new boot disk.

Abstract: An apparatus for correcting errors in information read from a memory unit, comprises a first and second memory, where primary and backup information are stored in predetermined addressable locations. The primary information and the backup information in corresponding locations are the same. A processor, commands a read of information stored in the memory unit, the read being a simultaneous read of the primary information and the corresponding backup information. A multiplexer, couples the output ports to the processor. The primary information read from the first and second memory and the backup information read from the first and second memory are coupled to the multiplexer. The first and second memory each indicate via a respective first and second error signal if an error is detected on the information just read from the first and second memory, respectively.

Abstract: In a method for securing the display on a screen of a workstation of mimic diagrams reflecting the status of a system connected to the workstation, a first counter is maintained in the system and a second counter is maintained in the workstation. The system periodically transmits to the workstation image data defining a mimic diagram reflecting the current status of the system, together with the first counter and a signature. In response, the workstation displays on the screen a mimic diagram based on the image data received and calculates a test value conditioned by the first and second counters, this value providing a basis for detecting a display error.

Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.

Abstract: Byte or symbol organized linear block codes are optimized in terms of reducing the number of ones in their parity check matrices by means of symbol column transformations carried out by multiplication by non-singular matrices. Each optimized symbol column preferably, and probably necessarily, includes a submatrix which is the identity matrix which contributes to low weight check matrices and also to simplified decoding procedures and apparatus. Since circuit cost and layout area are proportional to the number of Exclusive-OR gates which is determined by the number of ones in the check matrix, it is seen that the reduction procedures carried out in accordance with the present invention solve significant problems that are particularly applicable in the utilization of byte organized semiconductor memory systems. Reduced weight coding systems are also generated in accordance with weight reducing procedures used in conjunction with modified Reed Solomon codes.