Abstract: A reasoning method capable of easily describing a model of diagnosis, a diagnosis method based on the reasoning method and a fault diagnosis system for performing efficiently faulty component diagnosis. Basic knowledge of a domain for which a knowledge base is used, expert's heuristic knowledge and meta-level knowledge for determining a scheme of use of the basic knowledge and the heuristic knowledge are provided. Fault diagnosis is performed for an objective of interest by executing a combination of reasoning based on the basic knowledge and reasoning based on the heuristic knowledge, in accordance with the meta-level knowledge.

Abstract: A failure analysis of a semiconductor memory compares data written into and out of each cell of the semiconductor memory. When there is a disagreement, a "1" is written into a failure analysis memory. A disagreement signal is applied as a write command to column and row address fail count memories and is counted by a fail counter. The column address and row address fail count memories receive the column and row addresses, respectively. When the write command is applied to the column and row address fail count memories, the number of defective cells is read out of the memory addresses by a read modify write operation. A 1 is added by column and row adders to the number of defective cells read out, and the results are written into the column and row address fail count memories. The number of defective cells is read out of the column address fail count memory and compared with a number of row spare lines of the memory under test.

Abstract: A multiprocessor computer system includes fault tolerant power up logic for finding a functioning CPU to operate as logical CPU0. Each microprocessor has a physical location designation which remains constant. When the system is powered up, all of the CPUs except the CPU in physical slot 0 (CPU P0) are initially placed in an inactive sleep state. The microprocessor in physical location 0 performs its power on self test (POST), and if the CPU functions properly, the CPU is designated as logical CPU0 (CPU L0). The microprocessor then awakens the remaining CPUs and boots up the rest of the computer system. If CPU P0 is not functioning properly, after a given time period the system awakens the processor in the next physical location and repeats the process of testing the CPU. The process repeats until an operating microprocessor is found to perform the CPU L0 functions.

Abstract: Multiplex nodes (11, 12) connected via multiplex transmission lines (A, B and C), a voltage setting unit 16, which changes the voltage of the multiplex transmission line C to a specified value, a controller IC 14, which detects a failure in the multiplex transmission lines A and B, a protective circuit 15, which writes specified address data received from the controller IC 14 and key word data and sends a state signal corresponding to these pieces of data to the voltage setting unit 16, and a controller IC 14 which writes these pieces of data in a predetermined area of the protective circuit 15 are provided. The controller IC 14 detects a failure, the voltage setting unit 16 connects the specified multiplex transmission line C to a power supply or ground according to a state signal received from the protective circuit 15, thus changing the states of the multiplex transmission lines A and B.

Abstract: A circuit and method are provided for a pad efficient and speed efficient test of column leakage currents in silicon memory devices. Memory circuits are blocked into memory bit planes associated with individual I/O pins. Adequate testing requires that each column in each bit plane be tested for charge leakage characteristics. Rather than switching between I/O pins to test memory blocks associated with given pins, the switching circuitry is implemented on the silicon and is selectively coupled to the outputs of the bit planes on the chip. A single high voltage analog output pin is provided for test observations. This eliminates the need to ramp the testing system's voltages up and down and avoids the problems of hot switching between I/O pins.

Abstract: Retrying a command from a CCW in a data processing I/O system having a channel connected to a control unit in which the channel detects an error condition and requests the control unit to retry the current command of an I/O operation. The control unit then determines if the requested retry can be accomplished, and, if it can, sends a response back to the channel requesting the channel to initiate a retry. After receiving the response, the channel checks to determine if conditions are still present which allow a retry, and if they are, executes the current command to perform the retry. If the control unit determines that a retry cannot be accomplished, the control unit has the option to perform a unit check procedure. If the control unit determines that neither a retry nor a unit check can be accomplished, the control unit has the option to perform a selective reset function.

Abstract: A fault detection arrangement provides error detection and verification of generated address sequences for the execution of read/write operations in a storage subsystem. The arrangement also prevents corruption of data stored on the subsystem array module. Gray code counters located in the address path of the array module generate sequential addresses and associated parity for words of a block of data, based on a starting address received from a storage controller. As each address is generated and transferred to storage devices of the array, a parity checker regenerates parity information associated with the transferred address and compares that parity information to the parity information received from the counters. If an address error is detected, execution of the read/write operation is suppressed and the controller is immediately notified of the error.

Abstract: In a shift register latch scan string such as that employed in level sensitive scan design (LSSD) methodologies, primary input and/or primary output signal line connections are distributed in a substantially uniform fashion along the length of the shift register scan string configuration so as to provide a mechanism for testing for fault conditions existing along the scan string.

Abstract: A memory system in which fault tolerance is achieved utilizing redundant clocks. The redundant clocks are synchronized, and a voter is used to deselect nonmatching clocks, thereby avoiding clocking errors. A circuit is provided to ensure a nonoscillating clock provides an output level at a desired state. Another circuit is provided to ensure oscillation upon power up.

Abstract: A method for detecting JTAG errors in which components in a boundary scan path of a JTAG serial test bus connect a single bit bypass register into the scan path rather than the expected register when errors are detected. JTAG instruction signals are shifted into the scan path to determine whether an instruction error was received by a component. Data scanned into the component is prefixed by a header which is monitored by the JTAG control circuitry to detect any instruction errors. The combined data and header are padded by bits preceding the header to be equal to a multiple of a data register contained within the JTAG control circuitry. The least significant bit positions of the header and the padding bits are shifted out of the data register prior to the time that the header or first byte of the header should have been in the data register of the JTAG control circuitry such that the least significant bit of the data register is a 1, if no single error occurred, and is a 0 if a single error occurred.

Abstract: An emulation system used to debug software for a digital signal processor (DSP) includes a built-in digital signal analyzer which operates upon the same digital signals as those presented directly to and outputted by the DSP, bypassing the signal converters used to convert an input analog signal to digital format and the output digital signal to analog format. A host computer communicates with the digital signal analyzer via firmware in a control processor and personality board, or is alternately connected directly with the analyzer. Communications between the digital signal analyzer and the DSP are through the same contact probe as that used for the emulation software. The analyzer may be used to trigger a software function within the emulator based upon the real-time signal from the DSP, and is also capable of interpolating between successive digital values of an analyzed signal for display purposes.

Abstract: The control software and hardware in the tape drive control unit creates and manages a multiple level error detection and correction system to protect the data written on the magnetic tape. The helical scan data write circuits operate on the received stream of data records to produce two orthogonal error detection and correction codes on a scan group level. The data write circuit divides the received stream of data records into data segments, each of which contains a predetermined number of data bytes. A first of these scan group error codes is generated on a per data segment basis while a second scan group error is generated across multiple data segments. A third level error correction code is also used to protect an entire scan group rather than data on a per byte basis. The third level error correction code generator produces an error code over a predetermined number of sequentially written scan groups to enable the control unit to reconstruct an entire scan group if its data integrity is compromised.

Abstract: A memory module, parity bit emulator, and method which emulate storing and retrieving a parity bit from memory. The memory module includes a memory for storing a data word which is retrieved from the memory during the read cycle. The memory module also includes a parity bit emulator which includes a parity bit generator. The parity bit generator is responsive to the retrieved data word and generates in response a corresponding parity bit during the read cycle. The memory module also includes an input/output port for outputting the retrieved data word and the generated parity bit during the read cycle.

Abstract: A network interface, in particular for motor vehicles having at least two computers and having at least two bus lines ("0") includes by a monitoring circuit (100), which cooperates with an evaluation circuit to detect the operativeness of the bus lines and identify a faulty bus line and an emergency circuit (210,215) controlled by the monitoring circuit to connect the faulty bus line to an emergency potential. Even in the event of a short circuit, to the supply voltage U.sub.B or earth, of one of the bus lines connected to a terminating unit (OP1,R3; OP2,R4) or in the event of a defective driver stage (T10,T20) of a network substation connected to the bus lines, it is still possible to operate the comparator (K) of a receiver or signal evaluation circuit even with only one operational bus line. In this way, a particularly high operational reliability of the network interface is obtained.

Abstract: A microcomputer includes a program memory for storing program data, a program counter for addressing the program memory, an instruction decoder for decoding the program data read out from an address of the program memory addressed by the program counter, an electrically programmable nonvolatile memory for storing address data denoting an address of the program memory where program data to be corrected is stored, and correction program data, a comparator for comparing the output from the program counter with the address data stored in the nonvolatile memory and outputting a coincidence signal when a coincidence is found therebetween, and a program correction circuit for reading out the program data from the nonvolatile memory in response to the coincidence signal, and for supplying the readout data to the instruction decoder in place of the output from the program memory.

Abstract: A diagnostic apparatus for testing devices such as computer systems, and computer system components such as disk drives or printers. The device comprises a main unit, the main unit having a central processing unit for executing instructions, issuing commands, and receiving data from a first device. The apparatus also has a first peripheral unit coupled to the main unit, the first peripheral unit having ports for interfacing with the first device, the first peripheral unit being interchangeable with a second peripheral unit for interfacing with a second device. The apparatus also comprises a first non-volatile memory unit coupled to the main unit, the first non-volatile memory unit comprising a first set of tests for the first device, the first non-volatile memory unit being interchangeable with a second non-volatile memory unit comprising a second set of tests for a second device. These interchangeable parts are provided so that the user may test various types of hardware.

Abstract: A system and method for detecting a loss of a message transmitted between first and second address spaces of a computer system. The system includes a first sequence number adding part adding a first sequence number to a transmission message transmitted from the first address space to the second address space, a reception message loss detecting part detecting a loss of a reception message received from the second address space, using a second sequence number added to the reception message, and a reception sequence number notifying part notifying the second sequence number added to the reception message to the second address space as a response message.

Abstract: A triple modular redundancy computing system including three asynchronously connected processing elements, each having its own memory, a plurality of arbiters cross connecting processor elements for enforcing synchronization for tasks and for voting arbitration on output and without voting for inputs.

Abstract: A communication system comprising a communication path through which a message passes and, a plurality of communication apparatus, each apparatus includes a message transmission function to the communication path, and a read function for reading the message from the communication path. Each communication apparatus has a communication cumulative amount table so as to store the communication cumulative amount of messages transmitted by each communication apparatus as communication history data. The communication apparatus adds the latest communication cumulative amount in the communication cumulative amount table to a message which is transmitted to the communication path. The communication apparatus compares the stored communication cumulative amount table with the received communication cumulative amount. Thus, troubles of the communication subjects in the communication apparatus according to the result of the comparison can be detected.

Abstract: A method and apparatus for sequential decoding using the stack algorithm. A stack is used which is small in size and which has a leaky bottom. A counter stores the total count of nodes observed so as to abandon decoding if this count exceeds a fixed value. A comparator continuously compares the metric at the top of the stack with the largest metric lost from the bottom of the stack as stored in a memory. A small memory stores the path scanned through the logic tree, thereby directly providing the decoded block.