Abstract: A multi-memory apparatus, configured only with identical memory units with access to the common system bus, provides secure data identity in the event of various errors by using synchronous as well as parallel operation. A memory unit in a multi-memory apparatus includes a refresh request circuit, a bus control circuit, a bus-response circuit as well as a control circuit. A master refresh request circuit issues a memory-refresh request by using the bus clock and a backup refresh request circuit issues a memory-refresh request by a trigger from the master memory. A master bus control circuit responds to the system bus and a backup bus control circuit prohibits the unit from responding. A master bus-response control circuit allows the bus control circuit to respond to the system bus and changes mode between memory units from master/backup to backup/master in the event of an error detected in the master memory unit.

Abstract: A data input control device for a serial controller wherein a plurality of nodes each having one or a plurality of sensors connected thereto are serially connected to each other with a main controller included therein, the main controller delivers a predetermined data frame signal at a period sufficiently shorter than the variation interval of data detected by the nodes, and each node serves to add to the data frame signal the data from sensors connected to the node. The main controller compares the sensor data contained in the data frame signal inputted thereinto for predetermined times on receipt of a data frame signal, and takes thereinto the sensor data as true data only when the results derived from the comparisons performed by the predetermined times coincide with each other. Therefore, errors caused over the whole path through which the data outputted from the sensors are inputted into the main controller via the respective nodes can be detected.

Abstract: A method and apparatus are provided for detecting and correcting various data errors that may arise in a mass data storage apparatus comprising a set of physical mass storage devices operating as one or more larger logical mass storage devices. More particularly, there is provided a method and apparatus for determining, on restoration of power to a device set, whether or not a write operation was interrupted when power was removed, and for reconstructing any data that may be inconsistent because of the removal of power.

Abstract: An address pattern generator for generating regular addresses in a freely set aside area of the memory cell to be tested. The arrangement of the column address generator is structured the same as that of the row address generator wherein both the column address generator and the row address generator receive an add signal from a control circuit, address values from first and second maximum value registers and address values from first and second initial value registers. The column address generator has a comparator which compares an address to be supplied to the memory to be tested with the address value output from the first maximum value register and a selection circuit which selects address to be supplied to the memory using a signal output from the comparator.

Abstract: The BRANCH DECISION ENCODING SCHEME shown herein overcomes the limitations of a dedicated debug port on a single chip computer processor. A dedicated debug port resolves many of the problems associated with an add-on logic analyzer, except for its limitation of an eight bit data interface. The 8 bit port is required as a trade-off between the device I/O requirements and development tools. During real time program development, it is virtually impossible to monitor the 24 bit program counter through a port only a third as wide. The present invention solves this problem by taking advantage of the sequential characteristics of application programs. There is a discontinuity in the program counter in only a limited number of situations: branches, jumps, subroutine calls and returns from subroutines, exceptions and returns from exceptions, traps and return from traps, and loopbacks to the tops of loops.

Abstract: A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.

Abstract: In transaction processing systems, it is known for resource-updating operations within a transaction to be backed out at the request of an application program following detection of error conditions during processing of the transaction. If the error condition is very likely to recur, it may be undesirable for the operations request to be presented to the application exactly as before. A transaction-oriented data processing system and a method of transaction-oriented data processing are provided in which operation requests or data packets may be marked to be excluded from the effects of application-requested backouts.

Abstract: A memory storage verification device for use with a memory storage unit in which electrical signals stored in selected memory locations are periodically accessed by an external processor. The device includes a register for storing the address of a memory location in the memory storage unit having a stored electrical signal, a comparator for comparing the address stored in the register with an electrical signal from the memory storage unit providing the address of the memory location being accessed by the external processor, and a latch including a trigger coupled to the output port of the comparator. The input port of the latch is coupled to the memory storage unit and receives the electrical signal stored in the memory location being accessed when the trigger receives a signal from the comparator.

Abstract: In an address decision system in an ATM exchange, a table memory stores data showing relationships between VPI/VCI values and addresses. A latch circuit latches a VPI/VCI value contained in a cell transferred via a cell highway. A comparator circuit compares the VPI/VCI values stored in the table memory with the VPI/VCI value latched by the latch and generates a comparator output signal showing, in a normal operation, one of the addresses at which the VPI/VCI value from the latch circuit coincides with one of the VPI/VCI values in the table memory. An address decision unit encodes the comparator output signal and generates an encoded signal based on the comparator output signal. A decoder unit decodes the encoded signal and generates a decoded signal. A check unit receives the comparator output signal and the encoded signal and generates an error signal when the comparator output signal and the encoded signal do not match each other.

Abstract: A random access semiconductor memory having an array of memory cells is provided with an internal test circuit for testing the contents of rows of stored test pattern data which are read from the array in units of data rows, each read from an entire row of cells of the array. The test circuit can be based on a set of transistors which are respectively coupled to the bit lines of the cell array, for detecting coincidence between the states of all of the bits of a data row that is read out, or coincidence between the states of a predetermined set of the row bits.

Abstract: An analog Viterbi decoder realizes a part of the signal processing operations necessary to produce a decoded signal by, for example, calculation of branch metrics in branch metric calculation circuit, and addition, comparison, and selection an ACS circuit, using analog signal processes, to remarkably decrease the number of elements, and to realize a high speed Viterbi decoder with a relatively small size.

Abstract: Error detection and fault isolation mechanisms generally require separate capture latches to capture every occurrence of an error (for example from a parity checker or timeout counter) and an associated mask latch to temporarily or permanently block further detection of the same error. In the claimed invention, the mask latch is replaced by a single error control mechanism which is able to set and reset the error capture latches. The detected error is held in the capture latch, thus preventing further error capture, until a signal from the single error control mechanism resets the latch.

Abstract: A logic simulation apparatus which performs logic simulation of an operation of a logic circuit which includes at least a plurality of logic cells and a plurality of nets connecting the logic cells together, including a check circuit having at least one data input to which a data input signal is applied, a clock input to which a clock signal is applied, and an output. The check circuit compares the data input signal with a predetermined data value at a timing determined by the clock input signal and produces at its output a timing error detection signal based on the comparison. A memory cell is connected to the check circuit and has the data input signal applied to one input thereof, and the output signal of the check circuit applied to another input of said memory cell.

Abstract: In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, two cache units are employed. Each cache unit is dedicated to handling half-bytes of information and incorporates highly reliable data validating logic without the necessity for providing double word wide output busses from each BPU. This feature, which lowers the lead count to each VLSI chip, is obtained by dedicating each cache unit to handling half-bytes of information.

Abstract: In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, two cache units are employed. Each cache unit is dedicated to handling half-bytes of information and incorporates highly reliable data validating logic without the necessity for providing double word wide output busses from each BPU. This feature, which lowers the lead count to each VLSI chip, is obtained by dedicating each cache unit to handling half-bytes of information.

Abstract: A diagnostic system for diagnosing states of circuit elements is described, wherein scannable circuits can be scanned without disturbing the state of unscannable circuits or violating protocols of busses on which unscannable devices are attached. One unscannable device is a standardized microprocessor. A processor interface circuit is coupled between the microprocessor and scannable processor circuits, via a processor bus, to insulate the scannable processor circuits from the unscannable microprocessor. The processor interface circuit is also scannable, including memory elements which affect the bus, by preventing a scan when the bus is in use. A scan is prevented through the use of a maintenance request signal from a scan controller to the processor interface circuit, and one or more maintenance approval signals from the processor interface circuit to the scan controller.

Abstract: Data to be recorded on a magnetic disk is binary encoded including standard error control coding. The data is divided into contiguous blocks and mapped into a sequence of complex numbers according to a predetermined set of coding rules. The mapped data is then recorded on the odd and even tracks on the disk in substantially orthogonal assignments. The orthogonalization technique is used to reduce if not avoid entirely off track interference. Where it is desired to read data from an even track but the head infringes on one of its odd neighbors, the head reads a slightly weaker signal from the desired even track, because the head is not completely over it, and a weak signal from the neighboring odd track. The interfering signal from the odd track does not appear as noise in the even entries of the post inverse Fourier transform sequence, which is used for decoding.

Abstract: A fault-tolerant digital data processor includes three identical logic CPU boards connected to a voting bus and a system bus. The three boards are initially designated as a master board, a slave board 0 and a slave board 1. The master board drives the system bus and the two slave boards serve as backups in case the master breaks. The master board issues signals, at different instances with the aid of multiplexing, to the slave boards. On the slave boards, corresponding signals are compared and the result is broadcast to all three boards. When all three boards are compared equal, the master board remains as master. If there is a miscompare between one slave board and the master but not between the other slave board and the master, the master board remains master, and the slave board with which the miscompare occurred will be disabled after another miscompare. If a miscompare occurs between the master board and both slave boards, a re-execution of the previous cycle occurs.

Abstract: Control unit level reset operations in systems having switched point-to-point I/O interface topologies is accomplished by determining and storing channel path identification numbers (CHPID's) and control unit link addresses (CULA's) for each device in the system, scanning this stored data to find devices whose CHPID's and CULA's match the CHPID and CULA for a device or a control unit having a reported error, quiescing devices with such matching CHPID's and CULA's, issuing a control unit level reset command and reactivating the quiesced devices. For systems having both multidropped and switched point-to-point topologies, provision is made for preliminarily determining whether a given control unit reset can be performed on the control unit level.

Abstract: Intermodule testing in a computer system including a plurality of modules interconnected via a system bus is performed by means of a serial test bus which is incorporated into the computer system for testing components, for example integrated circuits, used to construct the modules of the computer system. Intermodule test data is maintained in memory on each of the modules and is accessible through operations of the serial test bus. Intermodule test data is retrieved by the serial test bus and used to set up the modules so that one module drives the system bus with test signals defined by test vectors included within the intermodule test data. The remaining modules are set up to receive the test signals. Tables are developed in accordance with the intermodule test data to define which test signals drive which system bus leads and also which receiving modules receive the test signals.