Abstract: In a hierarchical, multi-level storage system, recovery from intermittent storage hardware failures is supported by establishing hardware checkpoints at storage system interfaces and by duplication of subsystem hardware within units of the storage system. When error is detected at an interface, all levels of the storage system are quiesced and backed up to a point preceding the occurrence of the error. If a hardware failure causes an error, the system is quiesced while the failed hardware is reconfigured with control logic copied from duplicate hardware. A single restart command restarts system operation.

Abstract: An on-line adaptive distributed diagnostic method for use in an arbitrary network comprised of N nodes, where N is greater than or equal to 3. The algorithms of the present invention provide on-line diagnosis in the presence of node and link failure. In the network, each node is capable of executing an algorithm used in the diagnostic method to update a packet which communicates between network nodes.

Abstract: Error correction code ("CECC") generation within a directory or memory controller is distributed between generation of an ECC for the tag and status portions of a directory entry and then summed to produce the ECC bits for the directory entry. The ECC generation may be performed for entries with respect to a cache for a uniprocessor or multiprocessor system or for system memory within such a data processing system. The ECC generation of the present invention reduces by one or more cycles the required time utilized for updating a directory entry.

Abstract: A board-mounted memory array includes a plurality of memory modules, each module N bits wide by M bits long, the memory array including YM addresses of words that are XN bits long, where X and Y are integers. Each word is comprised of N bits from a common address value in each of X modules. The memory array includes memory interface logic mounted on the board which accesses the memory array in response to address signals. The memory interface logic is configured to use a first address procedure to access individually addressed words in the memory array at a first rate and, upon command, to use a second address procedure to sequentially access a span of contiguous addresses at a second, higher rate. A controller is coupled to the memory interface logic and enables application of address signals generated external to the board.

Abstract: A communication controlling apparatus comprising a transmission line error detecting circuit 30 which determines whether a transmission line error is detected or not in the data transmitted from its own node without immediately disabling a P-channel MOS transistor 20 or N-channel MOS transistor 21 as output gates when an error is detected in one of the transmission lines (BUS+line 11 or BUS-line 12), a sequence control circuit 31 which informs all the other nodes that the error is detected in its own node, and a selector 27 which determines whether the transmission line error detecting circuit 30 has detected or not the transmission line error in the transmit start (SOF) period and selects a differential comparator. The reliability of communication is improved when an error is detected in one of the transmission lines.

Abstract: An array controller implemented method and apparatus are provided for dynamically expanding a redundant array of independent disk drives (RAID) by adding any number M of direct access storage devices (DASDs) to the original array while maintaining data availability and system performance to an array user. A logical to physical address map (LPAM) of original array (LPAM-O) and of expanded array (LPAM-E) and initial array state information are established and stored. A selected domain of data blocks is defined for deferred access to an array user. Then the selected domain of data blocks is read using LPAM-O. Parity information is calculated with the read data of the selected domain of data blocks. Then the read selected domain of data blocks and the calculated parity information are written to the expanded array using LPAM-E.

Abstract: A redundant maintenance architecture for general purpose, digital computer systems. The architecture has both redundant maintenance controllers and redundant maintenance interfaces. This invention provides uninterrupted maintenance control over a distributed system despite any single hardware failure. This is accomplished by providing a low level hardware fault detection and correction apparatus which does not require expensive test hardware or software. The low level hardware apparatus detects faults within a primary maintenance controller or interface and transfer control of the maintenance functions of the computer system to a secondary maintenance controller and interface. All of this is accomplished on-the-fly and does not require that the computer system be switched into a test mode or otherwise interrupted from normal operation.

Abstract: A built-in self-test system and method for use in testing an integrated circuit. An integrated circuit (200) includes a self-test generator (210) that produces pseudo-random test vectors, each having fewer bits than a normal input signal applied to the integrated circuit. The normal signal comprises data and parity bits that are applied to a plurality of error detection and correction (EDAC) circuits (50) on the integrated circuit. Selected bits of the pseudo-random test vectors generated by the self-test generator are fanned out to provide the total number of bits of the data and parity signals, and a test signature is produced after a full set of test vectors have been processed by the EDAC. A signature analyzer (222) compares the test signature with a predetermined expected signature to determine if a fault has occurred in one of the EDACs in the integrated circuit. The self test can be made upon demand, or alternatively, can be run pseudo-concurrently with the normal mode, using cycle stealing.

Abstract: A method is disclosed, for use with a multiprocessing hardware mesh architecture including nodes and a network of interconnections between the nodes, for defining and implementing a target logical mesh architecture utilizing a given subset of the nodes and the interconnections of the hardware architecture. Typically, the hardware mesh architecture includes redundant nodes and interconnections, sot hat the target logical mesh architecture may be defined from the hardware architecture several different ways. As a consequence, the target logical mesh architecture may be defined even in the presence of faulty nodes or interconnections in the hardware architecture. Frequently, the logical mesh is defined in terms of some regular pattern of interconnections.

Abstract: An automatic testing apparatus includes an expert rule which is derived from expert knowledge and defines a tree of successively traceable nodes interconnected by decision branches which lead to a plurality of fault modes. Each of the nodes defines a particular test pattern and a corresponding expected value. One of the nodes is specified and a test pattern defined by the specified node is applied to an LSI chip under test and a result signal is derived therefrom. This result signal is compared with the expected value defined by the specified node to produce a comparison result. The tree of the expert rule is traced from the specified node to a subsequent node according to the comparison result and the subsequent node is specified instead of the previously specified node. The process is repeated as the tree is traced from one node to another until one of the fault modes is reached to identify a chip failure.

Abstract: The memory (RAM) of an electronically controlled franking machine containing data corresponding to postal value amounts is enclosed, together with a microprossor (CPU) on a mounting board in a lead-sealed casing. In the event of a defect of an element enclosed in such casing, the complete assembly unit comprising the mounting board and the casing is replaced. In order to be able to subsequently transfer in tamper-proof manner, the data from the memory to that of the new assembly unit, in a transceiver bus between the memory and the CPU, there are two plug units. One of these plug units is closed by a connector unit, so that during the operation of the franking machine the data flow is looped through the connector unit. A writing line, provided in addition to the transceiver bus, is used for reading in the working data during franking, so that it is not accessible via any plug unit.

Abstract: The invention provides a multi-stage architecture where the first stage is extremely wide and fast, but has a shallow depth which greatly reduces cost. A second stage provides a more conventional variable width/depth memory. Between the two stages is a programmable cross point switch matrix which determines which channels, of the many channels from the first stage, is to be connected as inputs to the second stage. Trigger comparisons may be performed in either or both stages.

Abstract: Optimizing of performance data in a data processing system is provided by the use of data filters and alarms. Statistics to be monitored are a conglomeration of both system statistics and statistics made available by application programs, both on local and remote data processing systems. The statistics are filtered using combinations of arithmetic and boolean operators. A single filtered condition can invoke multiple alarm responses, and multiple alarm conditions can trigger the same alarm response. Feedback of filtered statistics is provided so that such statistics can be monitored and recorded in the same manner as normal system statistics.

Abstract: In transmission lines with a redundant structure having a switching control communication channel, the fault status of a transmission line, communication channel data, and transmission line selection status are inputted into a memory as addresses, and the transmission line is switched and the switching control data is transmitted using the output data. By doing this, when a fault occurs and the current transmission line is switched to a spare transmission line, the switching is performed in a short time without the processing load of the CPU being increased.

Abstract: An interlocking system for a railway comprises a plurality of processors (A, B and C), the system having an input (1) for receiving input information and an output (2) for providing control information. Each of the processors is adapted to test itself to check that it is operating correctly and each of the processors is also adapted to test another of the processors to check that the other processor is operating correctly, each of the processors also being so tested by another of the processors. The system is shut down or put into a more restricted mode of operation if a fault in its operation is detected, either as a result of a processor's self-testing routine or as a result of one of the processors detecting that another processor is not operating correctly. This achieves the integrity of a "dual-channel" system with only a single "channel" of hardware.

Abstract: A computer implemented method for robustly copying pages to system managed storage in order to maintain data in a consistent state and in order to provide continuous access availability of the pages to executing applications. The method achieves data consistency by atomically shadow copying application referenced pages and amending directories in a failure independent medium on (1) an access path interrupt as well as on (2) a page update basis. Availability is enhanced by duplexing the pages and directories as part of the atomic shadow copying step.

Abstract: In a code transmitting method for transmitting an information code with an error detection or error correction code, a first error detection or correction code derived by sampling the information code diagonally on a matrix formed by two dimensionally arraying the information code is added to the matrix along a row direction, a second error detection or correction code derived by sampling, along the row direction, the code of the matrix having the first error detection or correction code added thereto is added to the matrix along the row direction, and the codes in the respective rows of the matrix having the second error detection or correction code added thereto are sequentially transmitted.

Abstract: A I/O controller which is connected to a plurality of I/O units and one spare I/O unit, controls a plurality of I/O units based on a command from a master unit, and allows a spare I/O unit to be used in place of an I/O unit where an abnormality is found, when an abnormality is found in any of a plurality of I/O units. This I/O controller outputs a decision about a normality at a time interval not in use for an operation when no command from a master unit (10) is being processed, after selecting I/O units (30) or a spare I/O unit (31). When the I/O controller outputs a decision of abnormality, the controller stores information about the abnormality in a preventive maintenance information storage register (25) as preventive maintenance information.

Abstract: A scan path test architecture for testing circuits using multiple system clocks with different frequencies includes a controller (16) for disabling the system clocks during a test cycle and a master clock for generating a signal frequency signal to each circuit module (10a-c), eliminating the need for partitioning scan paths between modules and synchronizing system clocks.

Abstract: The syntactic definition of a grammar for language statements is the basis for a method for automatically generating error messages and error recovery for the language statements. The grammar is used to produce a parser, an error message generator, and error recovery for the language statements. The error message generator is produced automatically along with a parser and provides an indication of alternative valid input symbols. The method also produces the automatic generation of expected symbols lists to achieve error message generation goals. The error recovery routines are also produced automatically along with a parser and provide an indication of where valid parsing continues in the event of error detection in the language statements. The method also uses the dynamic generation of sets of synchronization symbols to achieve error recovery goals.