Abstract: A method and apparatus are disclosed which act to prevent damage to stored data through the operation of a computer virus. The apparatus is preferably a plug-in card insertable to occupy a number of address locations within a computer system to be protected. At BIOS initialization of the computer system, the apparatus alters interrupt pointers, stored in RAM, to specific ROM functions, to point to locations within the apparatus. The apparatus can then monitor relevant interrupt requests for data change instructions wherein if data changes are intended, warning messages are provided to the computer user, who can then decide to continue the operation, or to abort which can prevent viral damage to stored data. In an alternative configuration, selected address locations can be continually monitored and the system shut down via a hardware reset in the event of unauthorized address location access.

Abstract: Test circuitry (90) is provided which includes a multiplexer (118) for selectively receiving multiple bit control words defining test functions to be executed by said test circuitry and for outputting data from said test circuitry. A plurality of digital data inputs (96) are provided for receiving multiple bit words of digital data and a plurality of analog data inputs (98) are provided for receiving analog data. A register (120) is coupled to multiplexer (118) for storing a one of the multiple bit words received by multiplexer (118). Control circuitry (122) is coupled to register (120) for controlling execution of the test function defined by the control word being held in register (120). First test circuitry (112) is coupled to digital data inputs (96) and control circuitry (122) for passing digital data words received at digital data inputs (96) to multiplexer (118) for output in response to a first control word of said control words being held in register (120).

Abstract: A method and apparatus for assisting in file recovery after a network fault uses a block state indicator in a client cache. After file data is stored in the client cache, the block state indicator is set to a client-cached state. After the file data is stored in a server cache, the block state indicator is set to a server-cached state. After the file data is stored in a non-volatile store attached to the server, the block state indicator is set to a stored state. If the data in server cache is lost or compromised due to a network fault, the data maintained in client memory is retransmitted. In a similar manner, file locks and file semaphores are re-established after a network fault.

Abstract: A microcomputer includes a program memory for storing program data, a program counter for addressing the program memory, an instruction decoder for decoding the program data read out from an address of the program memory addressed by the program counter, an electrically programmable nonvolatile memory for storing address data denoting an address of the program memory where program data to be corrected is stored, and correction program data, a comparator for comparing the output from the program counter with the address data stored in the nonvolatile memory and outputting a coincidence signal when a coincidence is found therebetween, and a program correction circuit for reading out the program data from the nonvolatile memory in response to the coincidence signal, and for supplying the readout data to the instruction decoder in place of the output from the program memory.

Abstract: In an apparatus having a main control section and sub-control sections connected to the control section through communication lines for executing desired operations by means of mutual intercommunication with the control section through the communication lines, first and second tri-state buffers are provided between the communication lines and the main control section and between the communication lines and the sub-control section respectively. The tri-state buffers short the communications lines by respective test signals output from the main control sections. When the test signal is not retransmitted to the control section through the communication lines shorted by the second tri-state buffer, anomalous operation of the sub-control section is detected. When the test sinal is not retransmitted to the control section through the communication lines shorted by the first tri-state buffer, anomalous operation of the main control section is detected.

Abstract: A sewer system for storing and supplying data to a destination. The server system includes a plurality of disk drives for storing data, a buffer memory for temporarily storing a portion of the data from the disk drives which is soon to be supplied, a reconstruction unit for reconstructing a portion of the data from at least one of the disk drives using a portion of the data from a plurality of the remaining disk drives so that at least one of the disk drives holding data belonging to the current parity group can be bypassed (either because that disk is faulty or because there are already many queued read-requests for it), a control unit for controlling the server system, and an output unit for outputting data from either or both of the buffer memory and the reconstruction unit. The server system prevents congestion problems from persisting, reduces buffering requirements, and provides load balancing and fault tolerance.

Abstract: A redundant array storage system in which a reserved area of a multiplicity of data storage units can be reliably synchronized, even if the synchronization cycle is interrupted by an unforeseen event or situation, such as sudden loss of power to the system or a component failure. By maintaining two groups or partitions of data storage units and updating only one group at a time, and by having a global table which provides information regarding which group of storage units is being updated, the present invention allows the system to reliably determine which of the data storage units maintain valid data in their reserved area and to conform the reserved areas of the other group of data storage units to the valid values, without the use of additional hardware devices.

Abstract: The present invention includes a connector that mates to the software-controllable parallel port output connector on a host device, a passive logic unit, and, preferably, a host-executable software program. The connector provides four loop-back connections: the AUTOFEED and FAULT pins are looped-together, as are the STROBE and BUSY pins, the INITIALIZE and SELECT pins, and the SELECT IN and PRINTER ERROR pins. The eight pins for data line output signals are input to the passive logic, which logic logically "OR's" the data line signals. The logical-OR output signal is fed back to the ACKNOWLEDGE pin of the connector, and signal ground pins on the connector are connected to ground. During testing, the connector and passive logic unit are connected to the host output parallel port, which typically is a 1284-compliant or other Centronics parallel-compatible port.

Abstract: The invention provides a method and apparatus for dynamic patching for run-time error checking. With the present invention, a program to be error checked is read into memory where a debugging module resides. Such in-memory copy of the program is scanned for load objects. The load objects comprise libraries used by the program being error checked, as well as the main routines of such program. Next, a list of patch sites in the load objects is created and these patch sites corresponds to address locations in the load objects to be patched. Address space is then allocated for sections of the patch area where calls to real checking code resides. Finally, patches are written out to the in-memory copy of the program to be error checked. The original instruction in a patch site is replaced with branch to patch area instruction and the original instruction displaced is stored in the patch site's corresponding section of the patch area.

Abstract: A method for automatically instrumenting a computer program for dynamic debugging. Such a computer program comprising source code written in a programming language for executing instructions on the computer. The source code is provided as a sequence of statements in a storage device to the computer. Each of the statements are separated into tokens representing either an operator or at least one operand. A parse tree is built according to a set of rules using the set of tokens. The parse tree is instrumented to create an instrumented parse tree for indicating that an error condition occurred in the computer program during execution. Object code is generated from the instrumented parse tree and stored in a secondary storage device for later execution using an error-checking engine that indicates error conditions present in the computer program.

Abstract: Restoration guide information is set on design of a network in data bases of terminal nodes of a current path. When a failure is detected during operation, establishment of a restoration path is tried by connecting a series of adjacent mergers in accordance with the restoration guides. If connection of adjacent mergers according to the restoration guides is impossible due to a multiple failure, the connection is tried by using associate mergers. When the restoration path is reestablished from an associate merger to the merger, similar processes are repeated. If two or more restoration paths are obtained during progress of restoration, one final restoration path is selected for use in the restoration in accordance with a predetermined reference. Link resources are released except for those connected in the final restoration path.

Abstract: A source-level run-time software code debugging instrument (10) includes target access probe ("TAP") (12) and communications adapter ("COMDAP") (14) that process emulation commands provided by source-level debugging software operating on a host computer. The TAP includes a TAP CPU (28) that receives target CPU input signals and delivers target CPU output signals for controlling the execution of software code by the target circuit in accordance with command signals provided by the host computer. The TAP also includes programmable logic cell array (24) and RAM (34). The TAP logic cell array routes command and data signals to and from the TAP CPU, and the RAM stores an in-circuit emulation ("ICE") program used by the TAP to operate the target circuit. The COMDAP is physically separate from the TAP and provides an interface between the host computer and the TAP. The COMDAP includes a programmable logic cell array (44) and an EPROM (46).

Abstract: The present invention utilizes a test circuit for receiving a reference clock signal and a sense clock signal and subsequently determining whether or not the reference and sense clock signals are either correct multiples of each other and/or in phase with each other. The test circuit may be located on the same chip with the microprocessor and the clock circuitry. The clock circuitry may include a phase locked loop ("PLL") circuit for receiving the reference clock signal and producing a sense clock signal for use by the remainder of the chip, wherein the sense clock signal is a multiple of the reference clock signal. The test circuit may count the number of cycles of the sense clock signal occurring within a predetermined amount of time, which may be proportional to the reference clock period. Alternatively, the sense clock signal and the reference clock signal may be passed through an XOR circuit and then the number of cycles counted within a predetermined time period.

Abstract: A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.

Abstract: Two identical streams of multi-bit symbols are received by a pair of storage elements, each having multiple locations and first and second pointer counters respectively identifying the locations at which received symbols are stored and from which stored symbols are retrieved. The storage elements are synchronized by providing each with a SYNC symbol that, when detected, causes the pointer counters to be placed in a predetermined (reset) state on one transition of a SYNC clock signal, releasing the pointer counters at the same time on a following transition of the SYNC clock signal.

Abstract: A radiation image information processing system subjects a radiation image to certain signal processing so as to obtain image signal and generates a visible image from the image signal. A support apparatus for the system is composed principally of a control unit, a radiation signal storage unit, a display and a keyboard. When a fault occurs in the radiation image information processing system, a support apparatus is connected to a control apparatus of the system. The fault of the system is detected by the support system, which generates a fault detection signal. An image signal which leads to occurrence of the fault or the like is stored in a memory and thereafter, the analysis of the fault is carried out based on the contents stored. In view of the analyzed contents, the fault is removed and hence the system is recovered.

Abstract: A fault tolerant clock system is provided by utilizing redundant clocks which are maintained in synchronization, with voting circuit serving to select one of a plurality of matching clock signals for use. A resistor is coupled in series between the crystal and the oscillation circuit in order to establish a desired duty cycle of the clock signal. A series connected diode capacitor network is connected between a node of the oscillator circuit and a power supply in order to ensure initiation of oscillation.

Abstract: A node operating in a network using the International Standard Organization (ISO) High-Level Data Link Control (HDLC) network protocol includes a mechanism for encoding information such that frames including the encoded information can be correctly interpreted by nodes operating in either of the standard 16-bit or 32-bit ISO-HDLC operating modes. The encoding mechanism produces a preliminary frame check sequence by encoding the information in an encoder using a generator polynomial G.sub.48 (x), which is a combination of the generator polynomials G.sub.16 (x) and G.sub.32 (x) which are used to produce frame check sequences for nodes operating in 16-bit or 32-bit modes, respectively. Before the information is encoded, the encoding mechanism sets the encoder to an initial condition using an initializing polynomial I.sub.48 (x). The preliminary frame check sequence is further encoded by adding to it a complementing polynomial C.sub.48 (x). The result is a 48-bit frame check sequence.

Abstract: A disk array data storage system has plural sets of storage disks connected to multiple corresponding I/O buses. Individual storage disks can be independently and asynchronously attached to or detached from corresponding interfacing slots of the I/O buses. The system has physical device drivers which represent the storage disks with respect to their connections to the interfacing slots of the I/O buses and physical device managers which represent the data kept on the storage disks. Interface drivers are provided to manage I/O transfers through corresponding I/O buses. When a particular storage disk is attached to or detached from an interfacing slot of an I/O bus, the interface driver corresponding to the I/O bus freezes all I/O requests that come from the physical device drivers that represent the storage disks in the set connected to the I/O bus. A configuration manager determines which interfacing slot the particular storage disk has been attached to or detached from.

Abstract: A system and method for analyzing large logic traces, with the system having an input for regular expressions, a generator for receiving the regular expressions and generating finite automata which use arithmetic/logic expressions that permit the use of a substantially infinite alphabet, an input for a large trace array, and an analyzer for searching the large trace array with the finite automata, with the analyzer producing results of the search.