Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: First and second inputs are associated with a port. Logic produces indications to software to cause the first input and second input to appear as a single input to the software. The logic produces an indication that no signal is present on either the first input or the second input. When a port bypass controller is coupled to the port, the logic produces an indication that both the first and second inputs are bypassed. When the port bypass controller is coupled to a Fibre Channel arbitrated loop, the logic produces a first signal to control whether the first input is included on the Fibre Channel arbitrated loop or bypassed, and a second signal to control whether the second input is included in the Fibre Channel arbitrated loop or bypassed.

Abstract: A USB system is capable of connecting, based on the function of constructing and connecting a virtual port by a virtual port constructing functional unit, a number of devices exceeding a prescribed number of tiers having a hub device in a connection topology of a host device—hub devices—a device of the USB system. When the host device addresses a device on its downstream side, the hub device acts as if it is a specified device by a proxy response functional unit including the hub device, and instantaneously performs a proxy response depending upon the situation that, for example, the device on its downstream side is not ready. This causes no problem associated with the turn-around time of the USB bus even if the prescribed number of tiers is exceeded.

Abstract: Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Entries in the cache have a host instruction address and tags that may include a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction. The cache may be a software cache apportioned by software from the main processor memory or a hardware cache separate from main memory.

Abstract: An arbitration elimination scheme for a bus. In a preferred embodiment, a programmable counter determines when a SCSI bus idle condition is reached and when a portion of an arbitration window for the bus has passed without participants. If there are no participants for arbitration, the SCSI initiator eliminates arbitration by asserting SEL and issuing initiator/target IDS. If any other device attempts to arbitrate at this time, the device sees SEL asserted and does not attempt to participate in arbitration.

Abstract: A peripheral component interconnect (PCI) device comprising a bus interface coupled to a component interconnect bus, a plurality of configuration space register sets, and virtual multiple-function logic. Each set of configuration space registers is associated with a function. The virtual multiple-function logic is coupled to the bus interface and the configuration space register sets. The virtual multiple-function logic provides access to a plurality of configuration space registers for a plurality of functions. The virtual multiple-function logic also enables a plurality of functions to share the bus interface and other internal logic.

Abstract: A connection is provided between logical macros to allow prioritization of operations in accordance with an arbitration scheme that distinguishes between operations based on such factors as priority or size of transaction. The invention allows connection of logical macros and prioritizes the appropriate operation for the resources available to optimize data throughput to optimize the utilization of multiple buses. A first arbiter manages data transmissions over a first communication bus. Arriving short or high-priority messages are transmitted over a second communication bus managed by a second arbiter, but only if the target logical macro is not the same as currently targeted by the first arbiter.

Abstract: A balanced approach is provided for interrupt coalescing, wherein interrupts of locking and other small size packets are maximized, while large data segment interrupts are minimized. Thus, the most desirable interrupt characteristics of both large data segments and smaller packets are achieved. Usefully, a data processing system has an adapter connecting the system to a network to receive incoming packets of varying size, the incoming packets respectively carrying messages to interrupt the system processor. Each incoming packet is analyzed, to determine whether or not it meets one or more prespecified criteria, at least a first criterion being related to the size of the incoming packet. The processor is immediately interrupted in accordance with the interrupt message carried by the analyzed packet, if the packet meets all the prespecified criteria. If the analyzed packet does not meet all of the prespecified criteria, the processor is interrupted in accordance with a specified interrupt coalescing technique.

Abstract: A method for accessing a device, such as a memory device and an interface device, by a processor is disclosed. The method involves the processor requesting access permission for the transfer of data. The bridge device grants access permission. The processor in response to the granting of access permission indicates that the processor is busy with the access. The processor also generates address and control signals for the access. The bridge device indicates that data is ready for transfer. A processing system including the processor and the bridge device is also disclosed.

Abstract: In one aspect, the invention is a tuned stub, SCSI topology comprising a SCSI bus, a breakout node on the SCSI bus, an external SCSI connector on the SCSI bus at a first point defined by a first propagation delay; an internal SCSI connector on the SCSI bus at a second point defined by a second propagation delay, the first and second propagation delays being substantially equal; a SCSI adapter electrically tapping the breakout node; and a terminator electrically tapping the breakout node.

Abstract: An integrated circuit for multi-port communications includes a high speed bus interface configured to interface to a core chipset through a high speed bus. The integrated circuit includes a serial mass data storage host adapter in communication with the high speed bus interface and configured to control a high speed mass data storage unit. The integrated circuit includes a high speed network controller in communication with the high speed bus interface and configured to control a network port.

Abstract: A control element for a mobile computer and a base station operable to functionally interact with the mobile computer, the control device being operable to detect when a mobile computer is interacting with the base station, and cause the mobile computer to perform a transition from an operating state to a sleep state. The mobile computer saves system context information when performing the transition. The control element is operable to cause the base station to perform a transition to an operating state in accordance with the system context information.

Abstract: A method and device and a bus system for generating at least one program interruption in at least one user of a bus system, at least one user storing a specifiable time value in at least one memory and the time value being compared with at least one base time, the at least one program interruption being triggered when the time value is equal to the base time.

Abstract: A method and system for forwarding interrupt requests from a source device to a destination device. A controller bridge receives data, from a source device, for a destination device and stores the incoming data in a data queue. An interrupt request is received from the source device for the destination device and forwarded to the destination device in response to completing a transfer of the data from the source device to the destination device. If data received from the source device for the destination device are pending in the data queue, the interrupt request is rejected and the source may resubmit the interrupt request at a later time. If additional data are received from the source device for the destination device, the data may be rejected in response to an interrupt pending in the interrupt queue from the source device for the destination device.

Abstract: The invention comprises an electronically secured inter-processor and virtual device communications system, with an input/output controller board, a multi-drop bus interface to multiple devices, and a parallel interface to an industry standard single board computer. The invention assigns a bus address and virtual identification number to each device and controls communications between the main central processing unit and the devices through a Plug-n-Play protocol.

Abstract: The bridge circuit comprises a first interface circuit operable to receive data from a data source at a first data rate; a second interface circuit operable to transmit the data to a data receiver at a second data rate; a data coupling circuit comprising: a synchronous coupling circuit operable to pass said data synchronously between the first interface circuit and the second interface circuit; and an asynchronous coupling circuit operable to pass the data asynchronously between the first interface circuit and the second interface circuit. Control logic is responsive to a synchronous transfer request signal to cause data to be passed by the synchronous coupling circuit once any data within the asynchronous coupling circuit has been emptied.

Abstract: The invention provides a method of transmitting data via a bus system coupling a plurality of bus participants with an arbitration procedure for the plurality of bus participants. The invention further enables bus arbitration during a first transmission since that the bus can be granted for a second transmission following the first transmission without wasting bus cycles. This is accomplished by determining the number of cycles remaining for the first transmission according to memory boundary and transmission packet boundary conditions.

Abstract: A method, apparatus, and computer instructions for counting interrupts by type. An interrupt count is incremented when a particular type of interrupt occurs. The count may be stored in the IDT or an interrupt count table outside the IDT. The interrupt unit increments the count each time a particular type of interrupt occurs. In the event of a potential count overflow, the mechanism of the present invention provides logic necessary to notify software in order to handle the overflow.

Abstract: Embodiments of the present invention provide a system and method for detecting if a device is coupled to an inter-integrated circuit (I2C) router and/or for resetting the device. The I2C router comprises a first I2C bus port having a presence line and/or a reset line. The I2C router further comprises a control logic coupled to and/or distributed within the first I2C bus port. The control logic may determine if a device is coupled to the I2C router as a function of a state of the presence line. The control logic may also determine if a reset condition exists. If a reset condition exists, the control logic changes the state of the reset line, thereby causing the device to reset itself.

Abstract: A module for inserting into a device with a rear panel comprising a crossed pair of electric lines with a first line and a second line is provided. The module can be connected to the lines of the crossed pair of electric lines by means of a respective plug-in connection. According to the invention, the module comprises a device that compensates for the crossing of the pair of electric lines in the rear panel.