Abstract: The present invention relates to a preparation method for patternization of metal electrodes in silicon solar cells. After disposing an amorphous silicon layer on a silicon substrate processed by diffusion, laser light is projected on the amorphous silicon layer for patternization, and transforming the amorphous silicon with low optical conductivity into polysilicon with high optical conductivity thanks to the recrystallization process of the laser light. Then, after immersing the amorphous silicon layer in plating liquid, metal electrode can be formed accurately at the spots of the amorphous silicon layer patterned by laser light. No external voltage is required; plating reaction is induced by illumination directly.

Abstract: A method of forming a semiconductor structure includes forming a photoresist layer over a substrate. The photoresist layer includes a first material removable by a removal process. The first material at a guard band portion of the photoresist layer along an edge portion of the photoresist layer is converted to a second material. The second material is not removable by the removal process. Also, the first material at the edge portion of the photoresist layer is not converted to the second material. The guard band portion is farther from a periphery of the substrate than the edge portion. The removal process is performed to remove the first material after the conversion of the guard band portion.

Abstract: A method for making a light emitting diode includes the following steps. A first epitaxial substrate having a first epitaxial growth surface is provided. A carbon nanotube layer is placed on the first epitaxial growth surface. An intrinsic semiconductor layer is grown on the first epitaxial growth surface epitaxially. A second epitaxial substrate is formed by removing the carbon nanotube layer, wherein the second epitaxial substrate has a second epitaxial growth surface. A first semiconductor layer, an active layer and a second semiconductor layer are grown on the second epitaxial growth surface in that order. A part of the first semiconductor layer is exposed by etching a part of the active layer and the second semiconductor layer. A first electrode is applied on the first semiconductor layer and a second electrode is applied on the second semiconductor layer.

Abstract: A method for fabricating a semiconductor device is disclosed. A first substrate is arranged over a second substrate. A wafer bonding process is performed on the semiconductor device. First regions of the device are enclosed by the bonding process. Second regions of the device remain exposed. One or more processes are performed on the exposed second regions, after performing the wafer bonding process. The one or more processes include a fill process that forms a fill material within the exposed second regions. An edge seal material is applied on the first and second substrates after performing the one or more processes.

Abstract: The present invention discloses an OLED panel and the OLED display device thereof. The OLED panel includes a metallic absorbing film, disposed on a light-out side of the OLED panel and grounded, for absorbing electromagnetic radiation produced by the OLED panel. The present invention uses the metallic absorbing film integrating on a glass substrate on a light-out side so that the metallic absorbing film absorbs the electromagnetic radiation from the OLED panel effectively and has the advantages of a simple structure and cheap material.

Abstract: A sintered connection is formed by pressing a semiconductor die against a substrate with a dried sintering material interposed between the substrate and the semiconductor die, the dried sintering material having sintering particles and a solvent. The substrate is heated to a temperature below a sintering temperature of the dried sintering material while the semiconductor die is pressed against the substrate to form local sinter connections between adjacent ones of the sintering particles. The local sinter connections collectively provide a stable joint that fixes the semiconductor die to the substrate prior to sintering. A sintered connection is then formed between the semiconductor die and the substrate from the dried sintering material, after the stable joint is formed.

Abstract: FinFETs in which a swelled material within the fin, typically an oxide of the fin semiconductor, causes strain that significantly increases charge carrier mobility within the FinFET channel. The concept can be applied to either p-type or n-type FinFETs. For p-type FinFETs the swelled material is positioned underneath the source and drain regions. For n-type FinFETs the swelled material is positioned underneath the channel region. The swelled material can be used with or without strain-inducing epitaxy on the source and drain areas and can provide greater strain than is achievable by strain-inducing epitaxy alone.

Abstract: A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate and a drain region defined thereon. A drift well is formed in the substrate adjacent to a second side of the gate. The drift well underlaps a portion of the gate with a first edge of the drift well beneath the gate. A secondary portion is formed in the drift well. The secondary portion underlaps a portion of the gate with a first edge of the secondary portion beneath the gate. The first edge of the secondary portion is offset from the first edge of the drift well. A gate dielectric of the gate comprises a first portion having a first thickness and a second portion having a second thickness. The second portion is over the secondary portion.

Abstract: A semiconductor device includes a pinned layer having a magnetic direction permanently set to a first direction, a tunnel insulating layer arranged on the pinned layer, a free layer arranged on the tunnel insulating layer and having a changeable magnetic direction, and a magnetic induction layer formed to surround the pinned layer and have a magnetic direction permanently set to a second direction different from the first direction.

Abstract: Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized.

Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.

Abstract: Semiconductor photovoltaic cells have surfaces that are textured for processing and photovoltaic reasons. The absorbing regions may have parallel grooves that reduce loss of solar energy that would otherwise be lost by reflection. One form of texturing has parallel grooves and ridges. The cell also includes regions of metallization for collecting the generated electrical carriers and conducting them away, which may be channels. The topography is considered during production, using a process that takes advantage of the topography to govern what locations upon will receive a specific processing, and which locations will not receive such a processing. Liquids are treated directly into zones of the cell. They migrate throughout a zone and act upon the locations contacted. They do not migrate to other zones, due to impediments to fluid flow that are features of the surface texture, such as edges, walls and ridges.

Abstract: FinFETs and fin isolation structures and methods of manufacturing the same are disclosed. The method includes patterning a bulk substrate to form a plurality of fin structures of a first dimension and of a second dimension. The method includes forming oxide material in spaces between the plurality of fin structures of the first dimension and the second dimension. The method includes forming a capping material over sidewalls of selected ones of the fin structures of the first dimension and the second dimension. The method includes recessing the oxide material to expose the bulk substrate on sidewalls below the capping material. The method includes performing an oxidation process to form silicon on insulation fin structures and bulk fin structures with gating. The method further includes forming a gate structure over the SOI fin structures and the bulk fin structures.

Abstract: There is provided a process for forming a layer of electroactive material having a substantially flat profile. The process includes the steps of providing a workpiece having at least one active area; depositing a liquid composition including the electroactive material onto the workpiece in the active area, to form a wet layer; treating the wet layer on the workpiece at a controlled temperature in the range of ?25 to 80° C. and under a vacuum in the range of 10?6 to 1,000 Torr, for a first period of 1-100 minutes, to form a partially dried layer; and heating the partially dried layer to a temperature above 100° C. for a second period of 1-50 minutes to form a dried layer.

Abstract: Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening.

Abstract: A method of making redistributed electronic devices that includes providing a wafer having a plurality of electronic devices, each electronic device having a pattern of contact areas forming die pads. The method also includes forming redistribution layers on a temporary substrate having a pattern of contact areas forming wafer bonding pads matching the die pads and a pattern of contact areas forming redistributed pads different than the wafer bonding pads, the wafer bonding pads are coupled to the redistributed pads through a plurality of stacked conductive and insulating layers. The die pads are coupled to the wafer bonding pads, and the temporary substrate is removed. The wafer and redistribution layers are then divided into a plurality of redistributed electronic devices.

Abstract: Methods for forming reduced gate resistance finFETs. Methods for a metal gate transistor structure are disclosed including forming a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Additional methods are disclosed.

Abstract: A method of forming a light emitting diode includes forming a transparent substrate and a GaN buffer layer on the transparent substrate. An n-GaN layer is formed on the buffer layer. An active layer is formed on the n-GaN layer. A p-GaN layer is formed on the active layer. A p-electrode is formed on the p-GaN layer and an n-electrode is formed on the n-GaN layer. A reflective layer is formed on a second side of the transparent substrate. A scribe line is formed on the substrate for separating the diodes on the substrate. Also, a cladding layer of AlGaN is between the p-GaN layer and the active layer.

Abstract: A light emitting device and a method of fabricating thereof are provided. The method of fabricating the light emitting device comprises: providing a substrate having a first major surface and a second major surface; forming a plurality of light-emitting stacks on the first major surface; forming an etching protection layer on each of the light emitting stacks; forming a plurality of holes by a discontinuous laser beam on the substrate; etching the plurality of holes; and slicing off the substrate along the plurality of holes to form a light emitting device. The light emitting device has a substrate wherein the sidewall of the substrate comprising a first area with a substantially flat surface and a second area with substantially textured surface.

Abstract: Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.