Abstract: A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.

Abstract: Methods are disclosed for extending floating gate regions within floating gate cells to form sub-lithographic features. Related floating gate cells and non-volatile memory (NVM) systems are also disclosed. In part, the disclosed embodiments utilize a spacer etch to form extended floating gate regions and floating gate slits with sub-lithographic dimensions thereby achieving desired increased spacing between control gate layers and doped regions underlying floating gate structures while still allowing for reductions in the overall size of floating-gate NVM cells. These advantageous results are achieved in part by depositing an additional floating gate layer over previously formed floating gate regions and then using the spacer etch to form the extended floating gate regions as sidewall structures and sub-lithographic floating gate slits. The resulting floating gate structures reduce breakdown down risks, thereby improving device reliability.

Abstract: Disclosed is a light emitting device. The light emitting device includes a substrate including a plurality of lead electrodes; a mold member including a cavity on the substrate; a light emitting chip in the cavity and on at least one of the lead electrodes; a connecting member for electrically connecting at least one of the lead electrodes to the light emitting chip; a resin member in the cavity; a spacer part between the lead electrodes, the spacer part including a material different from materials of the mold member and the resin member; and an adhesive film between the mold member and the substrate.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell architecture, with off-axis or laterally offset top electrode via (TEVA) and bottom electrode via (BEVA). Traditional RRAM cells having a TEVA and BEVA that are on-axis can cause high contact resistance variations. The off-axis TEVA and BEVA in the current disclosure pushes the TEVA away from the insulating layer over the RRAM cell, which can improve the contact resistance variations. The present disclosure also relates to a memory device having a rectangular shaped RRAM cell having a larger area that can lower the forming voltage and improve data retention.

Abstract: An light apparatus used in forming a solar cell includes a housing separate from other processing in a deposition processing system, a transport mechanism for carrying a solar cell into the housing after deposition of a front contact layer in the deposition processing system, and one or more light source elements arranged to apply light on the solar cell after deposition of the front contact layer. A method of making a solar cell includes forming a back contact layer on a glass substrate, forming an absorber layer on the back contact layer, forming a buffer layer on the absorber layer, and forming a front contact layer above the buffer layer, the glass substrate, back contact layer, absorber layer, buffer layer, and front contact layer forming a first module. The method includes applying a light source to the first module after forming the front contact layer separate from other processing.

Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract: According to one embodiment, the semiconductor element includes a semi-insulating substrate which has a first first-conductivity-type layer. The semiconductor element includes a first semiconductor layer. The first semiconductor layer contains non-doped AlXGa1-XN (0?X<1). The semiconductor element includes a second semiconductor layer. The second semiconductor layer contains non-doped or second-conductivity-type AlYGa1-YN (0<Y?1 and X<Y)). The semiconductor element includes a first major electrode and a second major electrode. The semiconductor element includes a control electrode provided on the second semiconductor layer between the major electrodes. And the first first-conductivity-type layer is provided under the control electrode.

Abstract: A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.

Abstract: A semiconductor device includes a pinned layer having a magnetic direction permanently set to a first direction, a tunnel insulating layer arranged on the pinned layer, a free layer arranged on the tunnel insulating layer and having a changeable magnetic direction, and a magnetic induction layer formed to surround the pinned layer and have a magnetic direction permanently set to a second direction different from the first direction.

Abstract: The present invention relates to the use of ternary nickel-containing metal alloys of the NiMR type (where M=Mo, W, Re or Cr, and R=B or P) deposited by an electroless process in semiconductor technology. In particular, the present invention relates to the use of these deposited ternary nickel-containing metal alloys as barrier material or as selective encapsulation material for preventing the diffusion and electromigration of copper in semiconductor components.

Abstract: Methods and apparatus for filling gaps on partially manufactured semiconductor substrates with dielectric material are provided. In certain embodiments, the methods include introducing a first process gas into the processing chamber and accumulating a second process gas in an accumulator maintained at a pressure level substantially highest than that of the processing chamber pressure level. The second process gas is then rapidly introduced from the accumulator into the processing chamber. An excess amount of the second process gas may be provided in the processing chamber during the introduction of the second process gas. Flowable silicon-containing films forms on a surface of the substrate to at least partially fill the gaps.

Abstract: A Group III-nitride-based enhancement mode transistor includes a heterojunction fin structure. Side faces and a top face of the heterojunction fin structure are covered by a p-type Group III-nitride layer.

Abstract: A semiconductor device includes a substrate, and a through electrode passing through the substrate. The semiconductor device has a pad region and a through electrode region. A pad covers the pad region, extends into the through electrode region, and delimits an opening in the through electrode region. A through electrode extends through the semiconductor substrate below the hole in the pad in the through region.

Abstract: A semiconductor light emitting element includes: an insulating substrate having a plurality of convex portions on a surface thereof; a plurality of light emitting element components having semiconductor laminated bodies that are laminated on the insulating substrate and are separated from one another by a groove that exposes the convex portions; and a connector connecting between the light emitting element components. The light emitting element components include a first light emitting element component and a second light emitting element component. The first light emitting element component is separated from the second light emitting element component with the groove in between, and has a first protrusion that protrudes toward the second light emitting element component. The connector includes a first connector having a shape that straddles the groove and that follows the convex portions, and has a straight section.

Abstract: Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins. Structures comprising bulk-type fins, SOI-type fins, and planar regions are also disclosed.

Abstract: A method of forming bumps of a semiconductor device with reduced solder bump collapse. The method includes preparing a semiconductor substrate in which pads are exposed externally from a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose the seed layer on the pads; forming pillars by performing a primary electroplating on a region exposed by the photoresist pattern; forming a solder layer by performing a secondary electroplating on the pillars; removing the photoresist pattern; forming solder bumps, in which solders partially cover surfaces of the pillars, by performing a reflow process on the semiconductor substrate; and removing portions of the seed layer formed in regions other than the solder bumps.

Abstract: A circuit board includes an insulation layer, an electrically conductive layer, and a solder mask layer. The insulation layer has a plurality of through holes passing through. The electrically conductive layer is formed on a surface of the insulation layer and covers the through holes. The electrically conductive layer has a plurality of portions exposed in the through holes to serve as a plurality of first conductive pads. The solder mask layer covers the electrically conductive layer and defines a plurality of openings to expose parts of the electrically conductive layer. Parts of the electrically conductive layer are exposed to the solder mask layer to serve as a plurality of second conductive pads. The second conductive pads are electrically connected to the first conductive pads respectively. This disclosure further relates to a chip package and a method of manufacturing the same.

Abstract: A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.

Abstract: A method for changing reflectance or resistance of a region in an optoelectronic memory device. Changing the reflectance of the region includes sending an electric current through the region to cause a reflectance change in the region. Changing the resistance of the region includes: projecting a laser beam at a first beam intensity on the region, resulting in the region changing from a first to a second different resistance value; electrically reading the second resistance value during which an optical signal carried by the laser beam has a first digital value; after electrically reading the second resistance value, the laser beam is projected at a second beam intensity on the region resulting in the region changing from the second to the first resistance value; and electrically reading the first resistance value of the region while the laser beam is being projected on the region at the second beam intensity.

Abstract: FinFETs and fin isolation structures and methods of manufacturing the same are disclosed. The method includes patterning a bulk substrate to form a plurality of fin structures of a first dimension and of a second dimension. The method includes forming oxide material in spaces between the plurality of fin structures of the first dimension and the second dimension. The method includes forming a capping material over sidewalls of selected ones of the fin structures of the first dimension and the second dimension. The method includes recessing the oxide material to expose the bulk substrate on sidewalls below the capping material. The method includes performing an oxidation process to form silicon on insulation fin structures and bulk fin structures with gating. The method further includes forming a gate structure over the SOI fin structures and the bulk fin structures.