Abstract: An apparatus includes an electrostatic discharge (ESD) protection device. In one embodiment, the protection device electrically coupled between a first node and a second node of an internal circuit to be protected from transient electrical events. The protection device includes a bipolar device or a silicon-controlled rectifier (SCR). The bipolar device or SCR can have a modified structure or additional circuitry to have a selected holding voltage and/or trigger voltage to provide protection over the internal circuit. The additional circuitry can include one or more resistors, one or more diodes, and/or a timer circuit to adjust the trigger and/or holding voltages of the bipolar device or SCR to a desired level. The protection device can provide protection over a transient voltage that ranges, for example, from about 100 V to 330V.

Abstract: Provided is a light emitting device package including: a plurality of lead frames disposed to be separated from one another; at least one light emitting device mounted on the lead frames and electrically connected to the lead frames through a bonding wire provided on a wire bonding pad, the wire bonding pad being disposed on the same surface as a light emission surface provided as an upper surface of the light emitting device; a body part formed to encapsulate and support the wire bonding pad, the bonding wire, the light emitting device and the lead frames, and having a reflective groove formed in an upper surface thereof to expose the light emission surface to the outside therethrough; and a lens part disposed on the body part, to cover the light emitting device.

Abstract: A method of fabricating a MEMS device is disclosed. A metal layer is provided over a first surface of a substrate including over an opening. The metal layer is patterned to define a membrane segment and a pad, with the membrane segment extending at least partially across the opening. An integrated circuit chip is attached over the opening to the membrane segment and pad, with the integrated circuit separated from an extending portion of the membrane segment by a gap. The integrated circuit chip includes a conductive member so that deflection of the extending portion relative to the conductive member can be measured as a change in capacitance.

Abstract: The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.

Abstract: A method for forming contact holes includes following steps. A substrate including a dense region and an isolation region is provided. A material layer is formed on the substrate. Sacrificed patterns are formed on the material layer in the dense region, wherein there is a first opening between the two adjacent sacrificed patterns. A spacer is formed on each of two sides of each of the sacrificed patterns, wherein the spacers are separated from each other. The sacrificed patterns are removed to form a second opening between two adjacent spacers. A planar layer is formed to fill up the second openings. A first slit is formed in the planar layer, wherein the first slit exposes a portion of the material layer under the second openings. The portion of the material layer exposed by the first slit is removed to form third openings in the material layer.

Abstract: The present invention relates to a gaming machine having a light source and one or ideally a series of lighting positions that are illuminated, via optical pathways that are suitably in the form of optical fibers that transmit light from the light source to the or each lighting position. The light source may have a light filter that operably controls the color and intensity of light illuminating from the lighting positions depending on the outcomes of the game being played. The present invention also relates to a network of the gaming machines and a centralized light source, wherein optical pathways, suitably in the form of optical fibers, transmit light from the light source to the light positions of two or more gaming machines. The network may also include a controller to control illumination of the lighting positions, including color of the light and intensity of the light based on data received from an outcome determiner of one or more of the machines of the network.

Abstract: A method that includes forming a masking element on a semiconductor substrate and overlying a defined space. A first feature and a second feature are each formed on the semiconductor substrate. The space interposes the first and second features and extends from a first end of the first feature to a first end of the second feature. A third feature is then formed adjacent and substantially parallel the first and second features. The third feature extends at least from the first end of the first feature to the first end of the second feature.

Abstract: A storage element includes: a storage layer which has magnetization perpendicular to a film surface, the direction of the magnetization being changed in accordance with information; a magnetization fixed layer which has magnetization perpendicular to a film surface used as a base of information stored in the storage layer; and an insulating layer of a nonmagnetic substance provided between the storage layer and the magnetization fixed layer. In the storage element described above, the magnetization of the storage layer is reversed using a spin torque magnetization reversal generated by a current flowing in a lamination direction of a layer structure including the storage layer, the insulating layer, and the magnetization fixed layer to store information, the storage layer is directly provided with a layer at a side opposite to the insulating layer, and this layer includes a conductive oxide.

Abstract: A thyristor device includes a semiconductor body and a conductive anode. The semiconductor body has a plurality of doped layers forming a plurality of dopant junctions and includes an optical thyristor, a first amplifying thyristor, and a switching thyristor. The conductive anode is disposed on a first side of the semiconductor body. The optical thyristor is configured to receive incident radiation to generate a first electric current, and the first amplifying thyristor is configured to increase the first electric current from the optical thyristor to at least a threshold current. The switching thyristor switches to the conducting state in order to conduct a second electric current from the anode and through the semiconductor body.

Abstract: A method of making an electronic device with a redistribution layer includes providing an electronic device having a first pattern of contact areas, and forming a redistribution layer on a temporary substrate. The temporary substrate has a second pattern of contact areas matching the first pattern of contact areas, and a third pattern of contact areas different than the second pattern of contact areas. The second pattern of contact areas is coupled to the third pattern of contact areas through a plurality of stacked conductive and insulating layers. The first pattern of contact areas is coupled to the second pattern of contact areas on the transferrable redistribution layer. The temporary substrate is then removed to thereby form a redistributed electronic device.

Abstract: A shadow masking device for use in the semiconductor industry includes self-aligning mechanical components that permit shadow masks to be exchanged while maintaining precise alignment with the target substrate. The misregistration between any two of the various layers in the formed structure can be kept to less than 40 microns.

Abstract: Methods and apparatus for reduced gate resistance finFET. A metal gate transistor structure is disclosed including a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Methods for forming the reduced gate finFET are disclosed.

Abstract: A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.

Abstract: A method for forming a hydrogen barrier liner for a ferro-electric random access memory chip including forming a first dielectric layer over a substrate; forming a gate over the first dielectric layer; forming a first aluminum oxide layer over the gate and the first dielectric layer; forming a second dielectric layer over the first aluminum oxide layer; etching a trench through the second dielectric layer and the first aluminum oxide layer to the gate; forming a hydrogen barrier liner over the second dielectric layer, the hydrogen barrier liner lining the trench and contacting the gate; forming a silicon dioxide layer over the first aluminum dioxide layer, the silicon dioxide layer substantially filling the trench; and substantially removing the silicon dioxide layer leaving a silicon dioxide plug in the trench.

Abstract: A high resolution active matrix backplane is fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed on a semiconductor-on-insulator substrate. The backplane layer is spalled from the substrate. A frontplane layer including passive devices such as LCDs, OLEDs, photosensitive materials, or piezo-electric materials is formed over the backplane layer to form an active matrix structure. The active matrix structure may be fabricated to allow bottom emission and provide mechanical flexibility.

Abstract: A semiconductor device includes a substrate, and a through electrode passing through the substrate. The semiconductor device has a pad region and a through electrode region. A pad covers the pad region, extends into the through electrode region, and delimits an opening in the through electrode region. A through electrode extends through the semiconductor substrate below the hole in the pad in the through region.

Abstract: When forming sophisticated transistors on the basis of a high-k metal gate electrode structure and a strain-inducing semiconductor alloy, a superior wet cleaning process strategy is applied after forming cavities in order to reduce undue modification of sensitive gate materials, such as high-k dielectric materials, metal-containing electrode materials and the like, and modification of a threshold voltage adjusting semiconductor alloy. Thus, the pronounced dependence of the threshold voltage of transistors of different width may be significantly reduced compared to conventional strategies.

Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes forming a fin structure on a semiconductor substrate and forming a gate structure on the fin structure. A capping layer is then formed over the semiconductor substrate, fin structure, and gate structure. The capping layer is patterned to form an opening exposing a second portion of the fin structure. An epitaxial layer is grown in the opening and on the second portion of the fin structure. At least one of a source region and a drain region is provided in the epitaxial layer. The method may continue to remove the capping layer.

Abstract: A semiconductor-centered MEMS device (100) integrates the movable microelectromechanical parts, such as mechanical elements, flexible membranes, and sensors, with the low-cost device package, and leaving only the electronics and signal-processing parts in the integrated circuitry of the semiconductor chip. The package is substrate-based and has an opening through the thickness of the substrate. Substrate materials include polymer tapes with attached metal foil, and polymer-based and ceramic-based multi-metal-layer dielectric composites with attached metal foil. The movable part is formed from the metal foil attached to a substrate surface and extends at least partially across the opening. The chip is flip-assembled to span at least partially across the membrane, and is separated from the membrane by a gap.

Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.