Abstract: A processing device initializes a drive strength value of a storage device in an electronic device to a first level. The processing device detects an operation to be performed on the storage device and executes the operation. The processing device monitors a bit error rate occurring in the storage device as a result of executing the operation and determines if the bit error rate satisfies a threshold value. In response to determining that the bit error rate satisfies the threshold value, the processing device increases the drive strength value of the storage device to a second level and re-executes the operation at the increased drive strength value of the storage device.

Abstract: A determination is made that bit errors of a selected data chunk stored in a computer memory are unable to be completely corrected using an initial error correction scheme. A plurality of other data chunks sharing a physical layout structure element of the computer memory with the selected data chunk is analyzed to identify one or more likely bit error locations of the selected data chunk aligned with one or more corresponding bit error locations of a threshold number of the analyzed other data chunks. An attempt is made to correct the bit errors of the selected data chunk based on the identified one or more likely bit error locations of the selected data chunk.

Abstract: The present disclosure describes various examples of a method, an apparatus, and a computer-readable medium for wireless communications (e.g., 5G NR) using hybrid automatic repeat request (HARQ). For example, one of the methods includes generating a first codeword based on a first code block length, transmitting a first signal using the first codeword, generating a second codeword with incremental redundancy information based on a second code block length, generating a third codeword with repetition of at least a portion of the first codeword based on a third code block length, and transmitting a second signal using at least the second codeword or the third codeword.

Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.

Abstract: Methods, systems, and devices for dynamically configuring transmission lines of a bus between two electronic devices (e.g., a controller and memory device) are described. A first device may determine a quantity of bits (e.g., data bits, control bits) to be communicated with a second device over a data bus. The first device may partition the data bus into a first set of transmission lines (e.g., based on the quantity of data bits) and a second set of transmission lines (e.g., based on the quantity of control bits). The first device may communicate the quantity of data bits over the first set of transmission lines and communicate the quantity of control bits over the second set of transmission lines. In some cases, the first device may repartition the data bus based on different quantities of data bits and control bits to be communicated with the second device at a different time.

Abstract: In some implementations, the present disclosure relates to a method. The method includes obtaining a set of weights for a neural network comprising a plurality of nodes and a plurality of connections between the plurality of nodes. The method also includes identifying a first subset of weights and a second subset of weights based on the set of weights. The first subset of weights comprises weights that used by the neural network. The second subset of weights comprises weights that are prunable. The method further includes storing the first subset of weights in a first portion of a memory. A first error correction code is used for the first portion of the memory. The method further includes storing the second subset of weights in a second portion of the memory. A second error correction code is used for the second portion of the memory. The second error correction code is weaker than the first error correction code.

Abstract: A method for reducing observed processing latency in networked communication, the method comprising: receiving a first portion of data, the data consisting of the first portion and a second portion; initializing data processing on the data after receiving the first portion of data and before receiving the second portion of the data; receiving the second portion of the data, the second portion of the data including error-detection code; performing error detection on the data based on the error-detection code; in response to the error detection indicating that the data is valid, finalizing data processing on the data and committing a data-processing result; and in response to the error detection indicating that the data is invalid, performing an error-correction process.

Abstract: An electronic controller includes: a logic circuit that is reconfigurable based on a reconfiguration instruction; an arithmetic unit that is configured in the logic circuit; a processing controller that transmits the reconfiguration instruction of the arithmetic unit to the logic circuit and that makes the reconfigured arithmetic unit execute predetermined operation; and a testing unit that executes an operation test for an arithmetic unit when the arithmetic unit is reconfigured, and that transmits the result of the operation test to the processing controller as a notice. Here, the processing controller makes the arithmetic unit execute predetermined processing based on the notice received from the testing unit.

Abstract: A decoder circuit includes an input to receive a first codeword encoded based on a quasi-cyclic low-density parity-check (QC LDPC) code. The first codeword includes a sequence of data arranged according to an order of columns in a first parity-check matrix associated with the QC LDPC code. A codeword reordering stage generates a reordered codeword by changing the sequence of the data in the first codeword based at least in part on a size of one or more circulant submatrices in the first parity-check matrix. An LDPC decoder generates a decoded codeword by decoding the reordered codeword based on a second parity-check matrix associated with the QC LDPC code. In some implementations, the second parity-check matrix may comprise a plurality of second circulant submatrices of a different size than the first circulant submatrices.

Abstract: A bit interleaving method involves applying a bit permutation process to a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N/M folding sections, each of the constellation words being associated with one of the F×N/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

Abstract: A request to store a first data is received. The first data and a first error-checking data are received. The first error-checking data can be based on a cyclic redundancy check (CRC) operation of the first data. A second data is generated by modifying the first data. A second error-checking data of the second data is generated by using the first error-checking data and a difference between the first data and the second data.

Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

Abstract: A memory system includes a packet protection circuit. The packet protection circuit includes a plurality of first CRC calculation circuits, each configured to calculate a CRC of M-byte data, where M is an integer greater than or equal to 1 and less than N, where N is an integer greater than or equal to 2, a first selector configured to output a CRC calculation result of one of the first CRC calculation circuits, and a second CRC calculation circuit configured to calculate a CRC of L-byte data, where L<N, where L=N×Z, and Z is an integer greater than 1, and add the CRC of L-byte data to the CRC calculation result output from the first selector to generate a first CRC that is compared with a second CRC to detect an error in a data packet transmitted between the host interface unit and the host device.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to interleave the parity bits and group-wise interleave a plurality of parity bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern to perform parity permutation; a puncturer configured to puncture at least some of the group-wise interleaved parity bit groups; and an additional parity generator configured to select at least some of the punctured parity bit groups to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a Low Density Parity Check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a plurality of modulation symbols, wherein the modulator is configured to map bits included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of each of the modulation symbols.

Abstract: A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.

Abstract: Technologies are provided in embodiments for improving efficiency of metadata usage by memory protection checks. One example method includes detecting a read request for data in a memory, initiating a first access to the memory for a data cache line containing the data, and initiating a second access to the memory for a metadata cache line mapped to the data cache line, where the metadata cache line contains two or more metadata items for two or more memory protection checks to be performed based on the data cache line. The method may further include performing the two or more memory protection checks using, respectively, the two or more metadata items from the metadata cache line. In more specific embodiments, the two or more memory protection checks are performed substantially in parallel.

Abstract: Systems and methods are provided for reducing error in data compression and decompression when data is transmitted over low bandwidth communication links, such as satellite links. Embodiments of the present disclosure provide systems and methods for variable block size compression for gridded data, efficiently storing null values in gridded data, and eliminating growth of error in compressed time series data.

Abstract: An apparatus includes an error correction component coupled to read recovery control circuitry. The error correction component can be configured to perform one or more initial error correction operations on codewords contained within a managed unit received thereto. The read recovery control circuitry can be configured to receive the error corrected codewords from the error correction component and determine whether codewords among the error corrected codewords contain an uncorrectable error. The read recovery control circuitry can be further configured to determine that a redundant array of independent disks (RAID) codeword included in the plurality of error corrected codewords contains the uncorrectable error, request that codewords among the error corrected codewords that contain the uncorrectable error are rewritten in response to the determination, and cause the plurality of error corrected codewords to be transferred to a host coupleable to the read recovery control circuitry.

Abstract: An encoder encodes input data utilizing a binary symmetry-invariant product code. The encoder includes circuitry including a half-size data array including D rows each having storage for H data bits (D=2×H+1). The encoder is configured to access bits of each row of the product code by reading a first H-bit data word from one of the D rows and a second H-bit data word across H different rows of the half-size data array. The encoder additionally includes a register configured to receive the bits of each row of the product code and to rotate the bits to obtain the rows of the product code and a row parity generator configured to generate row parity for each row of the product code. The encoder finally includes a column parity generator configured to generate, based on the row parity, column parities for the parity bits of all rows of the product code.