Abstract: A memory controller having improved wear-leveling performance controls a memory device including a plurality of memory blocks. The memory controller includes a read operation controller, a cell state determiner, and a read reclaim controller. The read operation controller controls the memory device to read selected memory cells of a first block among the plurality of memory blocks by using at least one reference voltage. The cell state determiner compares a number of memory cells among the selected memory cells that are read as first memory cell with a reference number corresponding to the at least one reference voltage, and generates cell state information indicating a memory cell degradation degree corresponding to at least one state. The read claim controller controls the memory device to copy data stored in the first block to a second block, based on a comparison between the memory cell degradation degree with a threshold degradation degree.

Abstract: A data writing method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving first data and second data from a host system; generating a first array error correcting code based on the first data, and generating a second array error correcting code based on the second data; programming a first group including the first array error correcting code into a first chip enable group by using a first programming mode; and programming a second group including the second array error correcting code into a second chip enable group by using a second programming mode.

Abstract: Apparatuses, systems, and techniques to compute cyclic redundancy checks use a graphics processing unit (GPU) to compute cyclic redundancy checks. For example, in at least one embodiment, an input data sequence is distributed among GPU threads for parallel calculation of an overall CRC value for the input data sequence according to various novel techniques described herein.

Abstract: Provided is an optical transmission/reception device including an error correction decoding unit (36) for decoding a received sequence encoded with an LDPC code, in which the error correction decoding unit (36) is configured to perform decoding processing using a parity check matrix (70) of a spatially-coupled LDPC code, which includes a plurality of parity check sub-matrices (71) combined with each other, in which the decoding processing is windowed decoding processing that uses a window (80) over one or more parity check sub-matrices (71), and in which a window size of the window (80) and a decoding iteration count due to throughput and requested correction performance are variable and input from a control circuit (12) connected to the error correction decoding device (36).

Abstract: A transceiver disposed on a first die in a bidirectional differential die-to-die communication system is disclosed. The transceiver includes a transmission section configured to modulate a first data onto a carrier signal having a first frequency for transmission via a bidirectional differential transmission line; and a reception section configured to receive signals from the bidirectional differential transmission line, the reception section including a filter configured to pass frequencies within a first passband that includes a second frequency, the first frequency being outside of the first passband. According to some embodiments, the reception section is configured to receive, via the bidirectional differential transmission line, modulated data at the second frequency at a same time that the transmission section transmits the modulated data at the first frequency.

Abstract: According to one embodiment, in a memory system, a memory controller is configured to execute a first operation of observing an optimum value of a read voltage and updating a set value based on the observation result of the optimum value, at a predetermined time point of a plurality of time points for updating the set value of the read voltage for a plurality of memory cells, and execute a second operation of updating the set value based on the set value updated at one previous time point without executing the observation of the optimum value, at a time point after one time point of the predetermined time point.

Abstract: A non-volatile solid-state storage is provided. The non-volatile solid state storage includes a non-volatile random access memory (NVRAM) addressable by a processor external to the non-volatile solid state storage. The NVRAM is configured to store user data and metadata relating to the user data. The non-volatile solid state storage includes a flash memory addressable by the processor. The flash memory is configured to store the user data responsive to the processor directing transfer of the user data from the NVRAM to the flash memory.

Abstract: A black box device for a vehicle includes a data storage system for recording event data fed to the black box from various vehicle sensors. The data storage system includes a memory having memory cells and a controller in communication with the memory. The controller is configured to receive data and determine one or more memory cells as a destination for the data to be written. The controller is configured to determine a wear level of the memory cells and select a subset of program states of the memory cells based on the wear level; and program the memory cells using respective subsets of program states for each respective memory cell.

Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

Abstract: In certain embodiments, a method includes repeatedly transmitting, by a first device, first data to a second device within a first time unit set. The first data is determined based on a first redundancy version and to-be-transmitted system bits. The first time unit set includes K time units, K?3, and K is an integer. The method further includes when a first condition is met, stopping, by the first device, transmitting the first data in the Mth time unit, where 2?M?K, and M is an integer.

Abstract: Systems and methods of communicating using asymmetric polar codes are provided which overcome the codeword length constraints of systems and methods of communicating that use traditional polar codes. Used herein, asymmetric polar codes refers to a polarizing linear block code of any arbitrary length that is constructed by connecting together constituent polar codes of unequal length. Asymmetric polar codes may be known by other names. In comparison to conventional solutions for variable codeword length, asymmetric polar codes may provide more flexibility, improved performance, and/or reduced complexity of decoding, encoding, or code design. The system and method provide a flexible, universal, and well-defined coding scheme and to provide sound bit-error correction performance and low decoding latency (compared with current length-compatible methods which can be used with current hardware designs).

Abstract: A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.

Abstract: An apparatus comprising non-volatile memory is configured to access a selected unit of encoded SLC data in the non-volatile memory during a first programming phase of a process of folding data stored at a single bit per memory cell to data stored at multiple bits per memory cell. The apparatus recovers the selected unit of SLC data based on redundancy data formed from units of SLC data that data include the selected unit of SLC data. The apparatus saves the recovered selected unit of SLC data to memory. The apparatus uses the saved recovered unit of SLC data during a second programming phase of folding the data stored at a single bit per memory cell to the data stored at multiple bits per memory cell, thereby saving considerable time in not having to again recover the SLC data using the redundancy data.

Abstract: Decoder is provided for memory systems. The decoder receives data from a memory device including a plurality of pages, each storing data, and decoding the data based on a type of a page in which the data is stored, among the plurality of pages and life cycle information indicating a current state of the memory device in its life cycle.

Abstract: An apparatus includes a non-volatile storage circuit that includes a primary copy of a data value in a first storage location and a redundant copy of the data value in a second, different storage location. The data value includes one or more bits. The apparatus further includes an error detection circuit configured to retrieve contents of the first and second storage locations in response to a request for the data value. The error detection circuit is further configured to perform an error correction operation on the retrieved contents of the first and second storage locations to generate a data output responsive to the request, and to perform an error detection operation to generate an error signal that indicates whether the retrieved contents of the first and second storage locations are different.

Abstract: Aspects of the disclosure relate to techniques for mitigating the decoding errors observed at the receiver as a result of puncturing symbols between consecutive subframes having the same transmission direction. To reduce the decoding errors, a plurality of transmission options, each including a number of resource blocks and a modulation and coding scheme (MCS), may be identified. In addition, each transmission option may be associated with one or more puncturing patterns that hinder decoding of a codeword at the receiver. The base station or user equipment (UE) may then select or modify at least one aspect of a scheduling decision involving the communication of the codeword in a given subframe of at least two consecutive subframes to minimize decoding errors. For example, a selected puncturing pattern or a transport block size associated with a selected transmission option may be modified.

Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.

Abstract: Provided herein may be an error correction decoder based on an iterative decoding scheme using NB-LDPC codes and a memory system having the same. The error correction decoder may include a symbol generator for assigning an initial symbol to a variable node, a reliability value manager for setting and updating reliability values of candidate symbols of the variable node in current iteration, a flipping function value calculator for calculating a flipping function value by subtracting a function value, related to the updated reliability values of remaining candidate symbols other than a target candidate symbol, from another function value, related to the updated reliability value of the target candidate symbol, in the current iteration, and a symbol corrector for changing the hard decision value to the target candidate symbol when the flipping function value is equal to or greater than a first threshold value in the current iteration.

Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.

Abstract: An exemplary semiconductor device includes an input/output (I/O) circuit configured to combine data corresponding to a write command received via data terminals with a first subset of corrected read data retrieved from a memory cell array to provide write data. The exemplary semiconductor device further includes a write driver circuit configured to mask a write operation of a first bit of the write data that corresponds to a bit of the first subset of the read data and to perform a write operation for a second bit of the write data that corresponds to the data received via the data terminals.