Abstract: Techniques for non-deterministic operation of a stacked memory system are provided. In an example, a method of operating a memory package can include receiving a plurality of memory access requests for a channel at a logic die, returning first data to a host in response to a first memory access request of the plurality of memory access requests, returning an indication of data not ready to the host in response to a second memory access request of the plurality of memory access requests for second data, returning a first index to the host with the indication of data not ready, returning an indication data is ready with third data in response to a third memory access request of the plurality of memory access requests, and returning the first index with the indication of data ready.

Abstract: A network element is configured to efficiently load balance packets through a computer network. The network element receives a packet associated with flow attributes and generates a Load Balancing Flow Vector (LBFV) from the flow attributes. The network element partitions the LBFV into a plurality of LBFV blocks and reorders the LBFV blocks to generate a reordered LBFV. The LBFV blocks are reordered based on a reordering sequence that is different from reordering sequences on other network elements in the computer network. The network element hashes the reordered LBFV to generate a hash key for the packet and selects a next hop link based on the hash key. The next hop link connects the network elements to a next hop network element in the computer network.

Abstract: Exemplary methods, apparatuses, and systems include receiving read operations. The read operations are divided into a current set of a sequence of read operations and one or more other sets of sequences of read operations. An aggressor read operation is selected from the current set. A data integrity scan is performed on a victim of the aggressor read operation. A read margin for a victim of the aggressor read operation is determined based on the error rate. An identifier associated with the aggressor is added to a cache and a counter for the identifier added to the cache is initialized based upon the determined read margin.

Abstract: A method, system, and apparatus for interleaving data including creating a buffer, writing input data, and reading output data out of the buffer.

Abstract: Devices and techniques for extended error correction in a storage device are described herein. A first set of data, that has a corresponding logical address and physical address, is received. A second set of data can be selected based on the logical address. Secondary error correction data can be computed from the first set of data and the second set of data. Primary error correction data can be differentiated from the secondary error correction data by being computed from the first set of data and a third set of data. The third set of data can be selected based on the physical address of the first set of data. The secondary error correction data can be written to the storage device based on the logical address.

Abstract: A one-time programmable (OTP) memory can be programmed over a number of programming sessions in which each programming session writes a different portion of the memory. To provide the OTP memory with data integrity check capability, the OTP memory stores multiple error detection code entries. With each programming session, a new error detection code is stored in a previously unused entry. When the OTP memory is read, the error detection code corresponding to the latest programming session is used to verify the content of the OTP memory.

Abstract: Systems and methods are described herein that allow information carrying bits of a transmission block to be placed at higher-reliability positions prior to transmission. An exemplary method includes generating a set of payload bits to be encoded for transmission, wherein the set of payload bits includes at least one known bit, interleaving the set of payload bits to generate an interleaved set of payload bits, wherein the interleaved set includes the at least one known bit in a predetermined position in the interleaved set, providing the interleaved set to a cyclic redundancy check (CRC) encoder to generate CRC-interleaved set of payload bits, wherein the CRC-interleaved set includes the at least one known bit in a predetermined position within the CRC-interleaved set, and encoding the CRC-interleaved set for transmission to a wireless device. Associated network nodes and wireless devices are included.

Abstract: The present disclosure relates to a semiconductor memory device. The semiconductor memory device includes memory cell array, error correction code (ECC) engine, refresh control circuit and control logic circuit. The memory cell array includes memory cell rows. The refresh control circuit performs a refresh operation on the memory cell rows. The control logic circuit controls the ECC engine such that the ECC engine generates an error generation signal by performing ECC decoding on sub-pages in at least one first memory cell row during a read operation. The control logic circuit compares an error occurrence count of the first memory cell row with a threshold value and provides the refresh control circuit with a first address of the first memory cell row as an error address based on the comparison. The refresh control circuit increases a number of refresh operations performed in the first memory cell row during a refresh period.

Abstract: A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently communicate or exchange information.

Abstract: Embodiments of the present disclosure relate to a method and device for interleaving data in a wireless communication system.

Abstract: According to one embodiment, a controller executes a first operation. The first operation includes reading a plurality of data units from a nonvolatile memory and executing a process on the read plurality of data units. The process includes an inverse conversion of a conversion applied to the plurality of data units and first decoding using the plurality of data units that has executed the inverse conversion. The controller acquires first information from one of the plurality of data units that has executed the first operation. The controller compares the acquired first information with an expected value of the first information and re-executes the first operation when the acquired first information and the expected value are not equal to each other.

Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

Abstract: A method includes a computing device of a storage network dispersed storage error encoding a plurality of data segments to produce a plurality of sets of encoded data slices. The method further includes the computing device obfuscating a first set of encoded data slices of the plurality of sets of encoded data slices using an obfuscating method to produce a first set of obfuscated encoded data slices. The method further includes the computing device outputting the first set of obfuscated encoded data slices for storage in the storage network.

Abstract: A storage device includes a nonvolatile memory device and a memory controller. The memory controller receives first data from the nonvolatile memory device based on a first read command, and performs error correction on the first data. When the error correction fails, the memory controller transmits a second read command and second read voltage information to the nonvolatile memory device, receives second data from the nonvolatile memory device, transmits a third read command and third read voltage information to the nonvolatile memory device, and receives third data from the nonvolatile memory device. The memory controller adjusts an offset based on the second data and the third data, transmits a fourth read command, fourth read voltage information, and the offset to the nonvolatile memory device, receives fourth data from the nonvolatile memory device, and performs a soft decision process based on the fourth data.

Abstract: An encoding method for encoding input information bits using an encoder implemented with concatenation of a CRC-? coder and a polar coder is provided. The method includes performing Cyclic Redundancy Check (CRC) coding on as many information bits as a determined number of CRC coding bits among input information bits and performing polar coding on the CRC-coded information bits and other information bits than the CRC-coded information bits.

Abstract: A method for transmitting a signal in a digital transmitter, includes generating at least one component for at least one service in a processor, wherein the at least one component relates to an audio component or a video component, generating at least one signaling data in the processor, wherein the at least one signaling data includes a broadcast stream ID for identifying one or more broadcast streams comprising the at least one service, first capability information for presenting all services in the at least one signaling data, a service ID for identifying the at least one service, and second capability information for presenting a specific service related to the service ID information and transmitting the signal comprising the at least one signaling data and the at least one component in a transmitting module, wherein the at least one component is carried via at least one physical layer pipe.

Abstract: A memory system controls a shift register memory and writes encoded data including a plurality of error correction code frames into a block of the shift register memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.

Abstract: A data processing method includes performing first equalization processing on a data stream that comprises a plurality of sub-data stream segments, performing segment de-interleaving on the data stream, separately performing first forward error correction (FEC) decoding on each sub-data stream segment in a data stream, performing, according to an equalization termination state of each sub-data stream segment, second equalization processing on each sub-data stream segment, performing second FEC decoding on the data stream, and outputting the data stream obtained according to the second FEC decoding in response to a preset iteration termination condition being met, or performing, in response to the preset iteration termination condition not being met, according to the equalization termination state of each sub-data stream segment obtained according to the first equalization, the second equalization processing on each sub-data stream segment obtained according to the second FEC decoding.

Abstract: This disclosure describes a programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets. This disclosure also describes techniques that include enabling data durability coding on a network. In some examples, such techniques may involve storing data in fragments across multiple fault domains in a manner that enables efficient recovery of the data using only a subset of the data. Further, this disclosure describes techniques that include applying a unified approach to implementing a variety of durability coding schemes. In some examples, such techniques may involve implementing each of a plurality of durability coding and/or erasure coding schemes using a common matrix approach, and storing, for each durability and/or erasure coding scheme, an appropriate set of matrix coefficients.

Abstract: A transmitter is provided, which includes: an encoder configured to generate a low density parity check (LDPC) codeword comprising information word bits, first parity bits and second parity bits based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a constellation mapper configured to map the interleaved LDPC codeword on constellation points, wherein the first parity bits are generated based on one of parity submatrices constituting the parity check matrix and the second parity bits are generated based on another of the parity submatrices constituting the parity check matrix.