Abstract: Methods and devices for puncturing of a polar code in a wireless network, wherein nested puncturing sets are determined based on a puncturing order which is determined based on a reliability order of information bit channels, so that only one index sequence needs to be stored for both the determination of the information set and the determination of the punctured set and so that puncturing does not require to adjust the information set at error prone indexes corresponding to puncturing indexes. The puncturing order might start with indexes corresponding to high reliability bit channels or to low reliability bit channels.

Abstract: A method is disclosed for use in an electronic device having a non-volatile storage device and a volatile storage device, the method comprising: retrieving a first encoded data packet from a first address in the non-volatile storage device; decoding the first encoded data packet to obtain a first data item and a first error code corresponding to the first data item, the first encoded data packet being decoded by using a first coding key that is associated with the first address; detecting whether the first data item is corrupt based on the first error code and an error correction function, storing the first data item at a first address in the volatile storage device when the first data item is not corrupt, and transitioning the electronic device into a safe state when the first data item is corrupt.

Abstract: A system is provided for performing erasure coding (EC) in a distributed storage system. During operation, the system can perform a partial encoding of a received first set of data fragments and second set of data fragments using EC to generate a first and a second EC codeword, respectively. The system can then distribute the first and the second set of data fragments among a set of storage nodes within the distributed storage system. The system can also distribute a first and the second set of intermediate parity fragments in the first and second EC codeword, respectively, among a subset of the storage nodes with alignments. The system can then merge the first and the second set of intermediate parity fragments to generate an overall parity for both the first and the second set of data fragments. The system can store, based on the alignments, each overall parity fragment in the overall parity in the corresponding subset of storage nodes.

Abstract: According to certain embodiments, a method by a transmitter is provided for adaptively generating precoder bits for a Polar code. The method includes acquiring at least one configuration parameter upon which a total number of precoder bits depends. The at least one configuration parameter comprising at least one of an information block length K, a code block length N, and/or a code rate R=K/N. The total number of precoder bits is determined, and the precoder bits for a code block are generated according to the determined total number of precoder bits. The precoder bits are placed within the code block.

Abstract: Embodiments of this application provide a method for encoding data in a wireless communication network. A communication device obtains an information bit sequence of a bit length K and a code length M. When M is greater than or equal to a first threshold and K is greater than or equal to a second threshold, the device divides the information bit sequence into p subsequences that are of an equal length K1. Then the device encodes each of the p subsequence to obtain p encoded subsequences. The device rate-matches each of the p encoded subsequences to obtain p rate matched subsequences, concatenates the p rate matched subsequences to obtain the output sequence of the code length M, then outputs the output sequence.

Abstract: A memory system includes a memory device including a plurality of memory cells, and a controller configured to access the plurality of memory cells. The controller includes a data read block configured to read first data from one or more pages included in first memory cells, determine a target memory cell subject to a compensation based on the first data, and read second data from one or more pages of second memory cells adjacent to the target memory cell, and an equalizer configured to convert the second data into symbol interfering data, check a probability of the first data from a lookup table according to the symbol interfering data, and determine the compensation on the first data based on the probability.

Abstract: A semiconductor device that conducts error detection and correction on multilevel data is provided. The semiconductor device includes a first gray code converter circuit, a second gray code converter circuit, a gray code inverter circuit, an ECC encoder circuit, an ECC decoder circuit, and a memory portion. When input data is retained in the semiconductor device, the first gray code converter circuit converts the input data to data in a gray code format, and the ECC encoder circuit generates inspection data in accordance with the data. The memory portion retains the input data and the inspection data. When the input data that has been retained is output from the semiconductor device, the second gray code converter circuit converts the input data read out from the memory portion into data in a gray code format, and the ECC decoder circuit conducts error detection and correction on the data and the inspection data read out from the memory portion.

Abstract: Obtaining or facilitating obtaining statistical performance of a storage system is described. For instance, a method comprises: dividing a value range of performance of a storage system into a plurality of adjacent sub-ranges, an upper limit value of each sub-range being a predetermined multiple of a non-zero lower limit value of the sub-range. The method also comprises: determining a distribution of a plurality of measurement values of the performance among the plurality of sub-ranges. The method further comprises: estimating, based on the distribution, a percentile of the plurality of measurement values corresponding to a predetermined percentage to indicate statistical performance of the storage system. As a result, statistical performance indicators of the storage system can be obtained with an acceptable error using a small amount of memory resources.

Abstract: One embodiment described herein provides a system and method for data compaction in a storage system comprising a plurality of storage nodes. During operation, in response to determining that data compaction is triggered, the system regroups valid data from a first set of data chunks stored in the storage system into a second set of data chunks such that a respective data chunk from the second set of data chunks comprises contiguous valid data slices. The system further performs error-correction-coding protection on the second set of data chunks. A physical location associated with a respective valid data slice remains unchanged subsequent to the error-correction-coding protection.

Abstract: Methods, systems, and devices for wireless communications are described. In some systems, a first device may transmit a signal to a second device including a number of error detection bits interleaved with a number of information bits. The second device may use the error detection bits to determine if the signal was received correctly, where each error detection bit may be associated with a set of information bits. The second device may progressively decode the signal and continuously perform an error detection calculation based on a first set of information bits associated with a first error detection bit. Based on the error detection calculation, the second device may calculate an expected error detection bit corresponding to the first error detection bit. The second device may compare the first error detection bit to the expected error detection bit. Other aspects and features are also claimed and described.

Abstract: A sensor apparatus includes a sensing means having one or more sensors. A processor unit processes data received from the one or more sensors. The processor unit has a processor, a memory which stores data used by the processor, and a memory controller that receives instructions from the processor and in response writes data output from the processor to the memory or retrieves data from the memory to the processor. The memory controller is configured to read and write data to one or more areas of the memory with ECC protection of the data and arranged to read and write data to one or more areas of the memory without applying any ECC protection. The sensor apparatus may be configured to process data captured from an antenna to identify the position and/or the range of at least one target in the line of sight of the antenna.

Abstract: Various embodiments include an on-die error correction code (ECC) system that preserves rectangular symbols of arbitrary size and shape, where the dimensions of the symbol are powers of two. Further, the on-die ECC system preserves symbols that include multiple rectangles of arbitrary size and shape, where the dimensions of each rectangle are powers of two, and where the vertical and horizontal offset between consecutive rectangles are also powers of two. If the on-die ECC system miscorrects a memory bit, then the miscorrection is constrained or restricted to the same symbol that includes the other error bits. Therefore, all error bits, including the miscorrected bit, are in the same symbol. As a result, a user ECC system, such as a symbol-based ECC system, can correct and detect any number of errors within a single symbol, even when the on-die ECC system miscorrects a memory bit.

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory having a plurality of blocks each including a plurality of memory cells, and a memory controller configured to calculate a bit error rate when reading data from a block of the blocks and obtain an equation representing temporal changes in the bit error rate for the block, and based on the obtained equation, determine, for the block, a timing for performing a next refresh operation by which data that have been written to the block are rewritten.

Abstract: Embodiments of the present invention provide a coding method, where the coding method includes: obtaining, based on a puncturing/shortening proportion P? and a prestored sequence S?, a constructed sequence S that has a length equal to a target code length M, where S? includes N? channel indexes sorted by channel reliability or channel capacity, and sorting of channel indexes in S is the same as or different from sorting of channel indexes in S?; and mapping a to-be-sent bit sequence to a channel corresponding to S. According to this method, an appropriate constructed sequence S may be generated based on different puncturing/shortening proportions to perform coding, thereby decreasing a bit error rate.

Abstract: Embodiments of this application disclose a data processing method and a data processing device. The method includes: obtaining a first to-be-processed bit sequence, where the first to-be-processed bit sequence is a transport block or a code block generated by performing code block segmentation on a transport block; encoding the first to-be-processed bit sequence to obtain a first encoded bit sequence; storing all or at least some bits of the first encoded bit sequence into a circular buffer; and outputting a first output bit sequence from the bits stored in the circular buffer. According to the method and the device that are provided in this application, rate matching can be implemented for a sequence generated through LDPC encoding.

Abstract: A memory apparatus and a data reading method thereof are provided. In the method, a plurality of memory cells of the memory apparatus are read to obtain read data, in which a threshold voltage of each memory cell is sensed and respectively compared with a first reference voltage and a second reference voltage to determine bit values. The first reference voltage and the second reference voltage are used to distinguish different states of the memory cell and the second reference voltage is larger than the first reference voltage. The bit values of the memory cells having the threshold voltage between the first reference voltage and the second reference voltage in the read data are gradually changed and syndromes of the changed read data are calculated. The read data is corrected according to values of the syndromes.

Abstract: A computer-implemented method, according to one embodiment, is for selectively storing parity data in different types of memory which include a higher performance memory and a lower performance memory. The computer-implemented method includes: receiving a write request, and determining whether the write request includes parity data. In response to determining that the write request includes parity data, a determination is made as to whether a write heat of the parity data is in a predetermined range. In response to determining that that write heat of the parity data is in the predetermined range, another determination is made as to whether the parity data has been read since a last time the parity data was updated. Furthermore, in response to determining that the parity data has been read since a last time the parity data was updated, the parity data is stored in the higher performance memory.

Abstract: The invention discloses a method and a receiving device of the Viterbi algorithm. The method is applicable for a Viterbi decoder that receives an output signal generated by a convolution code encoder processing an original signal. The convolution code encoder includes M registers and M is a positive integer greater than or equal to 2. The method includes the following steps. First, for the first to the Mth data of the output signal, the Viterbi decoder performs the add-compare-select operation based on the known M initial values of the M registers. Then, for the Mth-last to the last data of the output signal, the Viterbi decoder performs the add-compare-select operation based on the known last M bits values of the original signal, thereby reducing the computational complexity of the add-compare-select unit.

Abstract: A memory system includes a semiconductor storage device and a memory controller including a storage circuit that stores correction value for read voltages in association with the word line, and a control circuit that reads data from the memory cells, performs a correction operation on the read data to determine a number of error bits therein, determines the correction value for each read voltage based on the number of error bits and a ratio of a lower tail fail bit count and an upper tail fail bit count, and stores the correction values for the read voltages in the storage circuit. The lower tail fail bit count represents the number of memory cells in a first state having threshold voltages of an adjacent state, and the upper tail fail bit count represents the number of memory cells in the adjacent state having threshold voltages of the first state.

Abstract: A method for polar encoding includes: receiving a message including information bits; encoding the message using a first polar code to obtain a first codeword; and encoding the message using a second polar code to obtain a second codeword. The second codeword includes two parts, and the first part of the second codeword is same as the first codeword. The method for polar encoding also includes transmitting the first codeword to a receiver in a first transmission; and transmitting the second part of the second codeword in a second transmission without transmitting the first part of the second codeword when the receiver is unable to decode the message based on the first codeword.