Patents Examined by Guy J. Lamarre
  • Patent number: 11366939
    Abstract: A method includes a computing device of a storage network dispersed storage error encoding a plurality of data segments to produce a plurality of sets of encoded data slices. The method further includes the computing device obfuscating a first set of encoded data slices of the plurality of sets of encoded data slices using an obfuscating method to produce a first set of obfuscated encoded data slices. The method further includes the computing device outputting the first set of obfuscated encoded data slices for storage in the storage network.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: June 21, 2022
    Assignee: Pure Storage, Inc.
    Inventors: S. Christopher Gladwin, Thomas F. Shirley, Jr., Gary W. Grube
  • Patent number: 11361832
    Abstract: A storage device includes a nonvolatile memory device and a memory controller. The memory controller receives first data from the nonvolatile memory device based on a first read command, and performs error correction on the first data. When the error correction fails, the memory controller transmits a second read command and second read voltage information to the nonvolatile memory device, receives second data from the nonvolatile memory device, transmits a third read command and third read voltage information to the nonvolatile memory device, and receives third data from the nonvolatile memory device. The memory controller adjusts an offset based on the second data and the third data, transmits a fourth read command, fourth read voltage information, and the offset to the nonvolatile memory device, receives fourth data from the nonvolatile memory device, and performs a soft decision process based on the fourth data.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: June 14, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunseung Han, Seonghyeog Choi, Youngsuk Ra, Hong Rak Son, Taehyun Song, Bohwan Jun
  • Patent number: 11362682
    Abstract: An encoding method for encoding input information bits using an encoder implemented with concatenation of a CRC-? coder and a polar coder is provided. The method includes performing Cyclic Redundancy Check (CRC) coding on as many information bits as a determined number of CRC coding bits among input information bits and performing polar coding on the CRC-coded information bits and other information bits than the CRC-coded information bits.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: June 14, 2022
    Assignees: Samsung Electronics Co., Ltd., Sungkyunkwan University Research & Business Foundation
    Inventors: Hongsil Jeong, Sang-Hyo Kim, Jong-Hwan Kim, Daehyeon Ryu, Seho Myung
  • Patent number: 11349601
    Abstract: A method for transmitting a signal in a digital transmitter, includes generating at least one component for at least one service in a processor, wherein the at least one component relates to an audio component or a video component, generating at least one signaling data in the processor, wherein the at least one signaling data includes a broadcast stream ID for identifying one or more broadcast streams comprising the at least one service, first capability information for presenting all services in the at least one signaling data, a service ID for identifying the at least one service, and second capability information for presenting a specific service related to the service ID information and transmitting the signal comprising the at least one signaling data and the at least one component in a transmitting module, wherein the at least one component is carried via at least one physical layer pipe.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: May 31, 2022
    Assignee: LG ELECTRONICS INC.
    Inventors: Minsung Kwak, Kyoungsoo Moon, Jangwon Lee, Woosuk Ko, Sungryong Hong
  • Patent number: 11347584
    Abstract: A memory system controls a shift register memory and writes encoded data including a plurality of error correction code frames into a block of the shift register memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: May 31, 2022
    Assignee: Kioxia Corporation
    Inventors: Masanobu Shirakawa, Hideki Yamada, Marie Takada, Ryo Yamaki, Osamu Torii, Naomi Takeda
  • Patent number: 11342940
    Abstract: A data processing method includes performing first equalization processing on a data stream that comprises a plurality of sub-data stream segments, performing segment de-interleaving on the data stream, separately performing first forward error correction (FEC) decoding on each sub-data stream segment in a data stream, performing, according to an equalization termination state of each sub-data stream segment, second equalization processing on each sub-data stream segment, performing second FEC decoding on the data stream, and outputting the data stream obtained according to the second FEC decoding in response to a preset iteration termination condition being met, or performing, in response to the preset iteration termination condition not being met, according to the equalization termination state of each sub-data stream segment obtained according to the first equalization, the second equalization processing on each sub-data stream segment obtained according to the second FEC decoding.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: May 24, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zhiyu Xiao, Ling Liu, Liangchuan Li
  • Patent number: 11340985
    Abstract: This disclosure describes a programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets. This disclosure also describes techniques that include enabling data durability coding on a network. In some examples, such techniques may involve storing data in fragments across multiple fault domains in a manner that enables efficient recovery of the data using only a subset of the data. Further, this disclosure describes techniques that include applying a unified approach to implementing a variety of durability coding schemes. In some examples, such techniques may involve implementing each of a plurality of durability coding and/or erasure coding schemes using a common matrix approach, and storing, for each durability and/or erasure coding scheme, an appropriate set of matrix coefficients.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 24, 2022
    Assignee: Fungible, Inc.
    Inventors: Rajan Goyal, Abhishek Kumar Dikshit
  • Patent number: 11343017
    Abstract: A transmitter is provided, which includes: an encoder configured to generate a low density parity check (LDPC) codeword comprising information word bits, first parity bits and second parity bits based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a constellation mapper configured to map the interleaved LDPC codeword on constellation points, wherein the first parity bits are generated based on one of parity submatrices constituting the parity check matrix and the second parity bits are generated based on another of the parity submatrices constituting the parity check matrix.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Kyung-joong Kim, Hong-sil Jeong
  • Patent number: 11342942
    Abstract: An electronic device includes a replica delay circuit configured to generate a delayed error check signal by delaying a first error check signal including error information of first data stored in a first memory region. The electronic device also includes an error sum signal generation circuit configured to generate an error sum signal by summing a second error check signal including error information of second data stored in a second memory region and the delayed error check signal.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 24, 2022
    Assignee: SK hynix Inc.
    Inventor: Sun Myung Choi
  • Patent number: 11334427
    Abstract: A non-volatile dual in-line memory module (NVDIMM) instantiates first and second partitions of non-volatile memory. The first partition is reserved and is not accessible to an operating system instantiated. The second partition is accessible to the operating system. A processor detects a first bad memory location in the second partition, stores a first system physical address of the first bad memory location to a system bad memory locations list, and stores a first DIMM physical address of the first bad memory location to a first NVDIMM bad memory locations list in the first partition.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: May 17, 2022
    Assignee: Dell Products L.P.
    Inventors: Ching-Lung Chao, Shih-Hao Wang, Hsin-Chieh Wang
  • Patent number: 11336304
    Abstract: In one implementation, the disclosure provides a decoding system that concurrently executes a read sample combining recovery process and an iterative outer code (IOC) recovery process. Performing the read sample combining recovery process entails executing multiple rounds of logic that each provide for combining together different data samples read from a data block. The IOC recovery process is performed at least partially concurrent with the read sample combining recovery process and each round of the IOC recovery process is based on newly-updated data samples generated by the read sample combining recovery process.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: May 17, 2022
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Deepak Sridhara, Jason Bellorado, Ara Patapoutian, Marcus Marrow
  • Patent number: 11327835
    Abstract: In an embodiment, a storage device includes a multiplicity of data value memory cells and a multiplicity of check value memory cells, where at least one of the multiplicity of data value memory cells is assigned to two of the check value memory cells, and where at least one of the multiplicity of check value memory cells is assigned to two of the data value memory cells, and a correction circuit which is configured to output a corrected data value when reading out a selected data value memory cell of the at least one of the multiplicity of data value memory cells, based on a content of the selected data value memory cell and based on contents of the two check value memory cells assigned to the selected data value memory cell.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: May 10, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Georg Georgakos, Michael Goessel
  • Patent number: 11327839
    Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having improved original data recovery capability may include a memory device including a plurality of memory cells, and configured to perform a read operation on data stored in the plurality of memory cells according to read mode information, and to output read data associated with the read operation and a memory controller configured to receive the read data, change the read mode information when error correction decoding for the read data fails, and control the memory device to perform the read operation again according to the changed read mode information. The read mode information may include information on a data interface between the memory device and the memory controller.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: May 10, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyun Woo Lee
  • Patent number: 11321016
    Abstract: In a method of writing data in a memory device, a plurality of duplicated bit rows is generated by performing a first duplication operation in which a plurality of bits included in write data are copied by units of bits. A plurality of duplicated bit groups is generated by performing a second duplication operation in which the plurality of duplicated bit rows is copied by units of rows. The plurality of duplicated bit groups is stored into a plurality of memory regions included in the memory device, respectively. Each of the plurality of memory regions is a region that is simultaneously sensed during a data read operation.
    Type: Grant
    Filed: May 30, 2020
    Date of Patent: May 3, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Youngsun Song
  • Patent number: 11323206
    Abstract: A method may comprise transmitting a first signal derived from a first subset of a set of LDPC coded bits and transmitting a second signal derived from a second subset of the set of LDPC coded bits. The second subset may be selected from the set of LDPC coded bits based on a lifting size of an LDPC base graph. The method may further comprise receiving an indication of a first redundancy version. The transmitting the first signal may be in response to receiving the indication of the first redundancy version.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: May 3, 2022
    Assignee: IDAC HOLDINGS, INC.
    Inventors: Chunxuan Ye, Nirav B. Shah, Fengjun Xi, Kyle Jung-Lin Pan
  • Patent number: 11314587
    Abstract: A method of correcting one or more bit errors in a memory device includes retrieving a codeword from a memory device. The codeword includes a data and an error correcting code. The method further includes determining whether the one or more bit errors are present in the retrieved codeword and correcting the retrieved codeword for the one bit error in response to determining one bit error is present in the retrieved codeword. The method also includes flipping a bit of the retrieved codeword in response to determining a plurality of bit errors is present in the retrieved codeword and correcting the retrieved codeword for the plurality of bit errors based on the bit-flipped codeword.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 11316537
    Abstract: A fault-tolerant analog computing device includes a crossbar array having a number l rows and a number n columns intersecting the l rows to form l×n memory locations. The l rows of the crossbar array receive an input signal as a vector of length l. The n columns output an output signal as a vector of length n that is a dot product of the input signal and the matrix values defined in the l×n memory locations. Each memory location is programmed with a matrix value. A first set of k columns of the n columns is programmed with continuous analog target matrix values with which the input signal is to be multiplied, where k<n. A second set of m columns of the n columns is programmed with continuous analog matrix values for detecting an error in the output signal that exceeds a threshold error value, where m<n.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: April 26, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ron Roth, John Paul Strachan
  • Patent number: 11307804
    Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include an interface to receive read and write requests from an application on a host. Storage, including at least one chip, may store data. An SSD controller may process the read and write requests from the application. A configuration module may configure the SSD. Storage may include a reliability table which may include entries specifying configurations of the SSD and reliabilities for those configurations.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: April 19, 2022
    Inventors: Yang Seok Ki, Rekha Pitchumani
  • Patent number: 11309036
    Abstract: Systems and methods that may be implemented for that may be implemented to compensate for NAND flash memory voltage threshold (Vth) shift by using one or more designated calibration wordlines that are programmed into the NAND flash memory with a pre-defined data pattern. In one example configuration, the disclosed systems and methods may be automatically implemented by a SSD controller when needed to compensate for flash memory voltage threshold (Vth) shift that occurs, e.g., due to NAND memory cell charge loss due to power-off data retention over an extended period of time.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: April 19, 2022
    Assignee: Dell Products L.P.
    Inventors: Chai Im Teoh, Lip Vui Kan
  • Patent number: 11301326
    Abstract: A method and apparatus for performing dynamic recovery management regarding a RAID are provided. The method includes: writing a first set of protected data into a first protected access unit of multiple protected access units of the RAID, and recording a first set of management information corresponding to the first set of protected data, for data recovery of the first set of protected data; and when any storage device of multiple storage devices of the RAID malfunctions, writing a second set of protected data into a second protected access unit of the protected access units, and recording a second set of management information corresponding to the second set of protected data, for data recovery of the second set of protected data. Any set of the first set of protected data and the second set of protected data includes data and multiple parity-check codes.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 12, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: An-Nan Chang