Abstract: Provided is a method of fabricating a silicon germanium (SiGe) Bi-CMOS device. In the fabrication method, the source and drain of the CMOS device is formed using a silicon germanium (SiGe) heterojunction, instead of silicon, thereby preventing a leakage current resulting from a parasitic bipolar operation. Further, since the source and drain is connected with an external interconnection through the nickel (Ni) silicide layer, the contact resistance is reduced, thereby preventing loss of a necessary voltage for a device operation and accordingly, making it possible to enable a low voltage and low power operation and securing a broad operation region even in a low voltage operation of an analogue circuit.

Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A layer of bottom electrode/copper diffusion barrier material (136) is formed (16) within an aperture (128) wherein the capacitor (100) is to be defined. The bottom electrode layer (136) is formed via a directional process so that a horizontal aspect (138) of the layer (136) is formed over a metal (110) at a bottom of the aperture (128) to a thickness (142) that is greater than a thickness (144) of a sidewall aspect (148) of the layer (136) formed upon sidewalls (132) of the aperture (128). Accordingly, the thinner sidewall aspects (148) are removed during an etching act (18) while some of the thicker horizontal aspect (138) remains. A layer of capacitor dielectric material (150) is then conformally formed (20) into the aperture 128 and over the horizontal aspect (138).

Abstract: A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A lower bulk insulator layer, a capacitor dielectric layer, a cell plate conductor layer, and an upper bulk insulator layer are formed upon a semiconductor substrate. An etch removes the cell plate conductor layer, the capacitor dielectric layer, and the lower bulk insulator layer so as to form an opening terminating within the lower bulk insulator layer. A sleeve insulator layer is deposited upon the upper bulk insulator layer and within the opening. Another etch removes the sleeve insulator layer from the bottom surface within the lower bulk insulator layer. A still further etch creates a contact hole that exposes a contact. The contact can be upon a transistor gate, a capacitor storage node, or an active region on the semiconductor substrate.

Abstract: Methods of forming silicide layers of a semiconductor device are disclosed. A disclosed method comprises depositing a polysilicon layer, a buffer oxide layer, and a buffer nitride layer on a semiconductor substrate; forming a gate on the semiconductor substrate by removing some portion of the polysilicon layer, the buffer oxide layer, and the buffer nitride layer; forming sidewall spacers on the sidewalls of the gate; forming source and drain regions in the semiconductor substrate by performing an ion implantation process; forming a first silicide layer on the source and drain regions; depositing a first ILD layer over the semiconductor substrate including the gate and the first silicide layer; removing some portion of the first ILD layer to expose the top surface of the gate; and forming a second silicide layer on the gate.

Abstract: The present invention provides a method for fabricating a stacked capacitor array (1), which comprises a regular arrangement of a plurality of stacked capacitors (2), with a stacked capacitor (2) being at a shorter distance from the respective adjacent stacked capacitor (2) in certain first directions (3) than in certain second directions (4), comprising the following method steps: provision of an auxiliary layer stack (5) having first auxiliary layers (6) with a predetermined etching rate and at least one second auxiliary layer (7) with a higher etching rate on a substrate (8); etching of in each case one hollow cylinder (9) for each stacked capacitor (2) through the auxiliary layer stack (5) in accordance with the regular arrangement, with the auxiliary layer stack (5) being left in place in intermediate regions (10) between the hollow cylinders (9); isotropic etching of the second auxiliary layers (7) to form widened portions (11) of the hollow cylinders (9), without any second auxiliary layer (7) being le

Abstract: Methods of making non-volatile field effect devices and arrays of same. Under one embodiment, a method of making a non-volatile field effect device includes providing a substrate with a field effect device formed therein. The field effect device includes a source, drain and gate with a field-modulatable channel between the source and drain. An electromechanically-deflectable, nanotube switching element is formed over the field effect device. Terminals and corresponding interconnect are provided to correspond to each of the source, drain and gate such that the nanotube switching element is electrically positioned between one of the source, drain and gate and its corresponding terminal, and such that the others of said source, drain and gate are directly connected to their corresponding terminals.

Abstract: A method of forming (and apparatus for forming) a zirconium and/or hafnium-containing layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and one or more silicon precursor compounds of the formula Si(OR)4 with one or more zirconium and/or hafnium precursor compounds of the formula M(NR?R?)4, wherein R, R?, and R? are each independently an organic group and M is zirconium or hafnium.

Abstract: A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device (134) includes a heavily doped N-well drain region (70). A 20V, relatively high-power NMOS device (132) includes heavily doped P-type buried layers (76, 78) underneath the source (94) and drain regions (96) and spanning the gap between the P-well gate (90F) and adjacent P-well isolation regions (46, 50).

Abstract: A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.

Abstract: A solid electrolyte capacitor includes a capacitor element, an anode lead, and a cathode lead. The capacitor element includes a capacitor chip, an anode wire projecting from the capacitor chip, and a cathode electrode formed on outer surfaces of the capacitor chip. The anode lead is electrically connected to the anode wire, whereas the cathode lead is electrically connected to the cathode electrode. A method for making such a solid electrolyte capacitor includes a laser irradiation step for irradiating the anode wire with a laser beam, and a connection step for connecting the anode wire with the anode lead after the laser irradiation step.

Abstract: The present invention supplies a manufacturing method of a semiconductor device, which includes a non-contact inspection process capable of confirming if a circuit or circuit element formed on an array substrate is normally performed and can decrease a manufacturing cost by eliminating wastes to keep a defective product forming. An electromotive force generated by electromagnetic induction is rectified and shaped by using primary coils formed on a check substrate and secondary coils formed on an array substrate, whereby a power source voltage and a driving signal are supplied to circuits or circuit elements on a TFT substrate so as to be driven.

Abstract: The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate (1) made of silicon with a first hard mask layer (10; 10?) made of silicon oxide and an overlying second hard mask layer (15; 15?) made of silicon; providing a masking layer (30; 30?) made of silicon oxide above and laterally with respect to the second hard mask layer (15; 15?) made of silicon and above an uncovered edge region (RB) of the semiconductor substrate (1); providing a photoresist mask (25) above the masking layer (30; 30?) with openings corresponding from trenches (DT) to be formed in the semiconductor substrate (1); opening the masking layer (30; 30?) in a first plasma process using the photoresist mask (25), the edge region (RB) being covered by a shielding device (AR); opening the first hard mask layer (10; 10?) and second hard mask layer (15; 15?) in a second and third plasma process; and forming the trenches (DT) in the semiconductor substrate (1) in a fou

Abstract: The invention relates to a method for producing a bipolar transistor. A semiconductor substrate is provided that encompasses a collector area of a first conductivity type, which is embedded therein and is bare towards the top. A monocrystalline base area is provided and a base-connecting area of the second conductivity type is provided above the base area. An insulating area is provided above the base-connecting area and a window is formed in the insulating area and the base-connecting area so as to at least partly expose the base area. An insulating sidewall spacer is provided in the window in order to insulate the base-connecting area. An emitter layer which forms a monocrystalline emitter area above the base area and a polycrystalline emitter area above the insulating area and the sidewall spacer is differentially deposited and structured, and a tempering step is carried out.

Abstract: Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a metal silicon compound deficient of silicon bonding atoms on a dielectric material overlying a semiconductor substrate conductively doped for PMOS and NMOS regions. The metal silicon compound overlying the NMOS region is converted to a metal silicon nitride and the metal silicon compound overlying the PMOS region is converted to a metal silicide. NMOS transistor gate electrodes comprising metal silicon nitride and PMOS transistor gate electrodes comprising metal silicide can be formed.

Abstract: A method of forming PrXCa1-xMnO3 thin films having a PMO/CMO super lattice structure using metalorganic chemical vapor deposition includes preparing organometallic compounds and solvents and mixing organometallic compounds and solvents to form PMO and CMO precursors. The precursors for PMO and CMO are injected into a MOCVD chamber vaporizer. Deposition parameters are selected to form a nano-sized PCMO thin film or a crystalline PCMO thin film from the injection of PMO and CMO precursors, wherein the PMO and CMO precursors are alternately injected into the MOCVD chamber vaporizer. The selected deposition parameters are maintained to deposit the PCMO thin film species having a desired Pr:Ca concentration ratio in a specific portion of the PCMO thin film. The resultant PCMO thin film is annealed at a selected temperature for a selected time period.

Abstract: In the present invention, a reference conductive layer and a first surface conductive layer are respectively provided on a surface and a back face of a first base film. The first base film includes a first via hole penetrating the first surface conductive layer. After a first electroless plating layer and a first conductive material are sequentially grown on a surface of the first base film, a first coating conductive layer composed of the first electroless plating layer, the first conductive material and the first surface conductive layer, is etched to have a reduced thickness. Then, the first coating conductive layer is patterned to form a first wiring layer. In this manner, a desired pattern width can be obtained even in the case where the first coating conductive layer is patterned by isotropic etching such as wet etching.

Abstract: A manufacturing technology of a MOSFET having a shallow junction and a source and drain of a low resistance is provided. After having ion-implanted an As on the surface of a p type well forming a gate electrode, a surface protection layer and an energy absorber layer are deposited on a substrate. When the surface of the substrate is irradiated by a YAG laser beam of the wavelength of 1064 nm for one nano second to 999 nano seconds, a heat absorbed by the energy absorber layer is transmitted to the substrate in an ultra short time, and heats its surface to a melting temperature, and therefore, the impurity is activated, and an extension region of a low resistance is formed in an extremely shallow region of about 20 nm in depth from the surface of the p type well.

Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

Abstract: In the method, trenches are etched and, in between, bit lines (8) are in each case arranged on doped source/drain regions (3, 4). Storage layers (5, 6, 7) are applied and gate electrodes (2) are arranged at the trench walls. After the introduction of polysilicon, which is provided for the gate electrodes (2), into the trenches, the top side is ground back in a planarizing manner until the top side of the covering layer (16) is reached, and afterward a polysilicon layer (18), which is provided for the word lines, is applied over the whole area and patterned to form the word lines.

Abstract: A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.