Abstract: A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.

Abstract: Contamination of an interface of respective films constituting a TFT due to an contaminant impurity in a clean room atmosphere becomes a great factor to lower the reliability of the TFT. Besides, when an impurity is added to a crystalline semiconductor film, its crystal structure is broken. By using an apparatus for manufacturing a semiconductor device including a plurality of treatment chambers, a treatment can be made without being exposed to a clean room atmosphere in an interval between respective treatment steps, and it becomes possible to keep the interface of the respective films constituting the TFT clean. Besides, by carrying out crystallization after an impurity is added to an amorphous semiconductor film, the breakdown of the crystal structure of the crystalline semiconductor film is prevented.

Abstract: The semiconductor device comprises: an insulation film 72 formed over a silicon substrate 10, an insulation film 78 formed on the insulation film 72 and having opening 82, and conductor 84 formed at least in the opening 82. Cavity 88 having the peripheral edges conformed to a configuration of the opening 82 is formed in the insulation film 72. The cavity 88 is formed in the region between the electrodes or the regions between the interconnection layers so as to decrease the dielectric constant between the electrodes or between the interconnection layers, whereby the parasitic capacitances of the region between the electrodes or the region between the interconnection layers can be drastically decreased, and consequently the semiconductor device can have higher speed.

Abstract: The invention relates to an object (1) that is cut by means of a laser and a water beam and to further processing of the cut material. The object is glued on a carrier (3) that is provided with an adhesive and can be transparent for the radiation used in the water beam (7). The carrier can be a solid body and preferably a fibrous mat (3). Said body or mat is penetrated by the water beam. The object (1) or the cut material thereof is held on the carrier (3) before, during and after cutting through in such a way that said object or material does not change position. In a preferred embodiment, a silicon wafer is used as the object because of the high cutting exactness to be obtained. Other materials can also be used.

Abstract: A drain electrode wiring conductor through which a main current of a MOS transistor takes the form of a flat board, being inserted into a first side of the frame of a case, and extends along the first side. The source electrode wiring conductor also takes the form of a flat board, being inserted into the first side and a second side, and extends parallel to a drain electrode wiring conductor along the first side. The flow of the current in the drain electrode wiring conductor is opposite in direction to the flow of the current in the source electrode wiring conductor. With the configuration, the parasitic inductance of a semiconductor module including a plurality of MOS transistors can be reduced.

Abstract: A method for fabricating a bipolar junction transistor on a wafer is disclosed. The wafer has a N-type doped area and a plurality of isolated structures. A protection layer is formed on the wafer and portions of the protection layer are then removed to expose portions of the doped area. A P-type epitaxy layer is formed on the protection layer and the first doped area and then portions of the epitaxy layer and the protection layer are removed. An insulation layer is formed and at least a collector opening and emitter opening are formed within the insulation layer. Following that, a polysilicon layer is formed to fill the collector opening and the emitter opening. A spacer is formed beside the polysilicon layer and the epitaxy layer followed by performing a self-aligned silicidation process to form a salicide layer on the polysilicon layer and portions of the epitaxy layer.

Abstract: The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor device. The resistor includes first and second crystalline layers which may or may not differ from one another. One of the first and second crystalline layers comprises doped silicon/germanium, and the other comprises doped silicon. The transistor device and resistor can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The invention also includes processes of forming semiconductor constructions, and in particular aspects, includes processes of forming resistor constructions.

Abstract: Active electrode material, such as fibrillized blend of activated carbon, polymer, and conductive carbon, is pretreated by immersion in a sealing coating. After the active electrode material is dried, the coating seals micropores of the activated carbon or another porous material, thus preventing exposure of water molecules or other impurities trapped in the micropores to outside agents. At the same time, the sealing coating does not seal most mesapores of the porous material, allowing exposure of the mesapores' surface area to the outside agents. The pretreated active electrode material is used for making electrodes or electrode assemblies of electrical energy storage devices. For example, the electrodes may be immersed in an electrolyte to construct electrochemical double layer capacitors. Pretreatment with the sealing coating reduces the number of water molecules interacting with the electrolyte, enhancing the breakdown voltage of the capacitors.

Abstract: The present invention relates to a solid electrolytic capacitor having a masking structure in which the insulation between the anode part and the cathode part can be ensured without fail, to its production method, to a method for coating a masking agent on a solid electrolytic capacitor substrate, and to apparatus therefore. According to the present invention, the masking material covers the dielectric film on the metal material having valve action and sufficiently infiltrates into the core metal made of a metal having valve action while the solid electrolyte is masked by the masking material without fail, so that a solid electrolytic capacitor can be produced that has a reduced leakage current and a reduced stress generated at the reflow treatment or the like.

Abstract: There is disclosed a semiconductor storage device comprising a trench capacitor wherein a high dielectric-constant insulator is used and formation of a depletion layer in a capacitor electrode is suppressed. The semiconductor storage device comprises a trench formed in a semiconductor substrate, a high dielectric-constant insulator formed on an inner wall of the trench, a first electrode formed in the semiconductor substrate contacting with the high dielectric-constant insulator and containing dopants to provide conductivity, a second electrode formed to fill the trench and containing the same dopants at least at the same concentration as in the first electrode, and a trench capacitor which includes the first electrode, the high dielectric-constant insulator and the second electrode and in which a depletion layer capacitance ratio (C/C0) is 0.9 or more during an operation.

Abstract: A method is disclosed for fabricating a integrated device, such as a MEMS device. A first wafer is provided on an exposed surface with a layer of gold, gold alloy or gold compound. A second wafer is provided on its exposed surface with under-layer of gold, gold alloy or gold compound; and an over- of bismuth, bismuth alloy, a compound of bismuth, cadmium, cadmium alloy, a compound of cadmium compound, tin, tin alloy, or a compound of tin. The wafers are then brought into contact and bonded at their surfaces through the deposited layers.

Abstract: As disclosed herein, a semiconductor device includes a gate and a silicon substrate having a field region and an active region. A gate dielectric layer formed on the upper surface of the active region of the silicon substrate and on a gate dielectric layer. The gate may include first and second sidewall dielectric layers sequentially formed on sidewalls of the gate, epitaxial silicon layers formed at both sides of the gate on the silicon substrate, first LDD regions formed in the silicon substrate below the second sidewall dielectric layers, second LDD regions formed at one sides of the first LDD regions below the epitaxial silicon layers, source/drain regions formed under the second LDD regions, and silicide layers formed on the gate and the source/drain regions.

Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film having a first thickness in a first region on a semiconductor substrate, forming a first gate electrode on the first insulating film, and forming a second insulating film having a second thickness different from the first thickness on the semiconductor substrate and the first gate electrode. Then, the method includes forming a conductive film on the second oxide film and forming a first resist pattern and a second resist pattern respectively on the conductive film in the first region and on the conductive film of a second region different from the first region. Then, the method includes removing the conductive film by using the first resist pattern as a mask to form a second gate electrode covering the first gate electrode via the second insulating film and removing the conductive film by using the second resist pattern as a mask to form a third gate electrode on the second insulating film of the second region.

Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.

Abstract: A method of protecting surface mount capacitors from moisture and oxygen corrosion by applying a thermally curable pre-coat resin to a portion of the terminals of a capacitor and encapsulating the capacitor element(s) with a protective resin. The pre-coat resin is substantially rigid at ambient temperatures and flexible at elevated temperatures and is preferably a lactone-containing epoxy resin. The pre-coat resin may be applied to a solder coating-free portion of the terminals by brush or wiper prior to encapsulating the capacitor element(s) with the protective resin.

Abstract: The invention provides a method for fabricating a memory cell for storing electric charge, which has a substrate (101), which forms a first electrode, a trench-like recess (102) etched into the substrate (101), conductive material, which is provided as a projection in a central region of the trench-like recess (102) and spaced apart from the side walls (107) of the trench-like recess (102) and is in electrical contact with the substrate at the base (104) of the trench-like recess (102), a dielectric layer (108), which has been deposited on the side walls (107) of the trench-like recess (102), the base (104) of the trench-like recess (102) and the surfaces of the conductive material (105), and an electrode layer (110), which has been deposited on the dielectric layer (108) and forms a second electrode.

Abstract: This invention includes methods of forming capacitors. In one implementation, a first capacitor electrode material is formed over a substrate. The first capacitor electrode material is exposed to a nitrogen comprising atmosphere effective to form a dielectric silicon and nitrogen comprising material on the first capacitor electrode material. The dielectric silicon and nitrogen comprising material is exposed to an aqueous fluid comprising a base and an oxidizer. The aqueous fluid has a pH greater than 7.0. After the exposing to the aqueous fluid, an aluminum oxide comprising capacitor dielectric material is deposited over the first capacitor electrode material. A second capacitor electrode material is formed over the aluminum oxide comprising capacitor dielectric material. Other aspects and implementations are contemplated.

Abstract: A method for creating a semiconductor structure is provided. In accordance with the method, a semiconductor substrate (101) is provided over which is disposed a sacrificial layer (103), and which has a thin single crystal semiconductor layer (105) disposed over the sacrificial layer (103). An opening (107) is then created which extends through the semiconductor layer (105) and into the sacrificial layer (103). The semiconductor layer (105) is then epitaxially grown to a suitable device thickness, thereby resulting in a device layer. The semiconductor layer is grown such that the resulting device layer extends over the opening (107), and such that the surface of the portion of the device layer extending over the opening is single crystal silicon.

Abstract: A fabrication of a capacitor in a semiconductor is simplified by using nitrogen plasma in forming an aluminum nitride layer functioning as an insulation layer on the aluminum layer disposed in a capacitor region. Subsequently, a planarized IMD (inter-metal dielectric) layer is obtained, facilitating via etching process.

Abstract: Method for the production of a semiconductor structure comprising a plurality of gate stacks on a semiconductor substrate which serve as control electrodes for a respective selection transistor of a corresponding memory cell comprising a storage capacitor. Gate stacks are provided next to one another on the substrate provided with a gate dielectric wherein the gate stacks have a lower first layer made of polysilicon, an overlying second layer made of metal silicide, and an upper layer made of silicon nitride. A sidewall oxide is formed on uncovered sidewalls of the first and second layers of the gate stacks, and at least partly the sidewall oxide is removed on those sidewalls of the gate stacks serving as a control electrode which are remote from the associated storage capacitor. Silicon nitride sidewall spacers are then formed on the gate stacks.