Abstract: The invention concerns a method which consists in forming on a substrate (1) coated with a dielectric material layer (3) provided with a window (3a), a stack of successive layers alternately of germanium or SiGe alloy (4, 6, 8) and polycrystalline silicon (5, 7, 9); selective partial elimination of the germanium or SiGe alloy layers, to form an tree-like structure; forming a thin layer of dielectric material (10) on the tree-like structure; and coating the tree-like structure with polycrystalline silicon (11). The invention is useful for making dynamic random-access memories.

Abstract: The present invention provides a fabrication method for a semiconductor structure in a substrate, the semiconductor structure having at least two regions that are to be patterned differently. A fabrication of a patterned first region in the substrate, so that the semiconductor structure has a non-patterned second region and the patterned first region, is followed by a deposition of a cover layer that grows over the patterned first region, so that the cover layer above the patterned first region forms a closure, which covers over the patterned first region. This is followed by a fabrication of the patterned second region, the patterned first region remaining protected at least by the closure of the cover layer. The final step effected is a removal of the cover layer above the semiconductor structure, which now has two differently patterned regions.

Abstract: A micro-electro-mechanical system (MEMS) device includes a mirror having a top surface with trenches, a beam connected to the mirror, rotational comb teeth connected to the beam, and one or more springs connecting the beam to a bonding pad. The mirror can have a bottom surface for reflecting light. Stationary comb teeth can be interdigitated with the rotational comb teeth either in-plane or out-of-plane. Steady or oscillating voltage difference between the rotational and the stationary comb teeth can be used to oscillate or tune the mirror. The comb teeth can have a tapered shape.

Abstract: A method for assembling and integrating microstructures (pills) onto a substrate. A plurality of patterned recesses are formed on the substrates, the recesses having transverse cross-sections and openings of specific shapes. A hard magnetic layer is deposited at the bottom of each said recess. A guide is positioned over the substrate, the guide having patterned hole shapes matching the shapes of the openings to the patterned recesses with which the holes mate. A collection of the pills is placed atop the guide. The said collection includes members with cross-sections matching the shapes of the openings to the recesses, and each pill is coated at one end with a soft magnetic layer. A moving magnetic field is applied to the collection of pills to agitate the pills, and effect a magnetic attraction between the layers at the ends of the pills and the soft magnetic layer at the bottom of the recesses.

Abstract: A method for a semiconductor process includes correlating yield loss for the performance of a processing step in a semiconductor manufacturing process with the mechanical placement of the semiconductor substrate and, based on the correlation, placing semiconductor substrates in a position with sufficient placement precision to reduce yield loss below a predetermined threshold.

Abstract: An object of the present invention is to provide a method for conducting electric activation of an electric double layer capacitor, the method making it possible to increase the electrostatic capacitance and to decrease the internal resistance. The method is for conducting electric activation of an electric double layer capacitor in which nonporous carbonaceous electrodes containing graphite-like fine crystalline carbon are soaked in an organic electrolytic solution. The method at least comprises: charging the electric double layer capacitor at a constant current until the interelectrode voltage reaches a predetermined voltage which is not lower than the electrostatic capacitance developing voltage but lower than the rated voltage; conducting constant voltage charging for a predetermined time during which ions of solutes in the organic electrolytic solution are conceived to be adsorbed uniformly on the surface of the fine crystalline carbon at that predetermined voltage.

Abstract: A method for fabricating a vertical offset structure that forms a complete vertical offset on a wafer includes a first trench forming step of forming first trenches on a wafer; a first etching step of performing a first patterning for determining etching positions of second and third trenches by depositing a first thin film on the wafer, performing a second patterning for temporarily protecting the etching position of the third trench by depositing a second thin film on the first thin film and the wafer, and then forming the second trenches by etching the wafer; a second etching step of forming a protection layer on side surfaces of the second trenches and then vertically extending the second trenches by etching the wafer; a third etching step of removing the second thin film and then forming the third trench by etching a position from which the second thin film is removed; and a fourth etching step of horizontally extending the second trenches vertically extended at the second etching step and the third tren

Abstract: A method of forming a magnetic random access memory (MRAM) using a sacrificial cap layer on top of the memory cells and the structure resulting therefrom are described. A plurality of individual magnetic memory devices with cap layers are fabricated on a substrate. A continuous first insulator layer is deposited over the substrate and the magnetic memory devices. Portions of the first insulator layer are removed at least over the magnetic memory devices and then the cap layers are selectively removed from the magnetic memory devices, thus exposing active top surfaces of the magnetic memory devices. The top surfaces of the magnetic memory devices are recessed below the top surface of the first insulator layer. Top conductors are formed in contact with the active top surfaces of the magnetic memory devices. In an illustrated embodiment, spacers are also formed along the sides of the magnetic memory devices before the first insulator layer is deposited.

Abstract: Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.

Abstract: The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a stress inducing pattern on a backside of a microelectronics wafer and growing a gate oxide layer on a front side of the microelectronics wafer in the presence of a tensile stress caused by the stress inducing pattern.

Abstract: Methods for patterning a magnetic cell junction and a topography used for and/or resulting from such methods are provided. In particular, a method is provided which includes etching portions of a topography adjacent to a patterned photoresist layer to a level within a cap film of the topography, removing etch residues from the topography and subsequently etching the remaining portions of the cap film to expose an uppermost magnetic layer. Another method is provided which includes patterning a dielectric mask layer above a patterned upper portion of a magnetic cell junction and ion milling a lower portion of the magnetic cell junction in alignment with the mask layer. An exemplary topography which may result and/or may be used for such methods includes a stack of layers having a dual layer cap film arranged above at least two magnetic layers spaced apart by a tunneling layer.

Abstract: A method for minimizing measuring spot size and noise during film thickness measurement is provided. The method initiates with locating a first eddy current sensor directed toward a first surface associated with a conductive film. The method includes locating a second eddy current sensor directed toward a second surface associated with the conductive film. The first and second eddy current sensors may share a common axis or be offset from each other. The method further includes alternating power supplied to the first eddy current sensor and the second eddy current sensor, such that the first eddy current sensor and the second eddy current sensor are powered one at a time. In one aspect of the invention, a delay time is incorporated between switching power between the first eddy current sensor and the second eddy current sensor. The method also includes calculating the film thickness measurement based on a combination of signals from the first eddy current sensor and the second eddy current sensor.

Abstract: A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is greater within the capacitor electrode-forming material than is a second set of the openings. Conductive first capacitor electrode material is formed therein. A sacrificial retaining structure is formed elevationally over both the first capacitor electrode material and the capacitor electrode-forming material, leaving some of the capacitor electrode-forming material exposed. With the retaining structure in place, at least some of the capacitor electrode-forming material is etched from the substrate effective to expose outer sidewall surfaces of the first capacitor electrode material.

Abstract: A method for fabricating a ferroelectric memory having memory cells arranged in arrays, wherein an Al2O3 film (2), a Pt film (3), a PZT film (4) and IrO2 film (5) are formed on an interlayer insulation film. At the time of forming a top electrode, the IrO2 film (5) is patterned using a resist mask having a part extending in the row direction, and then patterned using a resist mask having a part extending in the column direction. Consequently, a top electrode of the IrO2 film (5) having a rectangular plan view is formed at the intersection of these resist masks.

Abstract: A micromechanical sensor and, in particular, a silicon microphone, includes a movable membrane and a counter element in which perforation openings are formed, opposite to the movable membrane via a cavity. The perforation openings are formed by slots, the width of which maximally corresponds to double the spacing defined by the cavity between the membrane and the counter element.

Abstract: A method of manufacturing a structure in which a substrate can be removed easily from a structure that has been formed on the substrate by using a film forming technology. The method of manufacturing a structure includes the steps of (a) forming an intermediate layer on a substrate; (b) forming a structure including a brittle material layer on the intermediate layer by at least using a spray deposition method of spraying material powder toward the substrate, on which the intermediate layer is formed, to deposit the material powder; and (c) removing the substrate from the structure.

Abstract: A method is provided in which a first oxide layer is deposited on a silicon substrate and etched to form openings. A first silicon epitaxial layer is grown on the substrate in the openings, forming first active regions, a second oxide layer is deposited thereon, and the first and second oxide layers are etched such that the first oxide layer is wholly removed and the second oxide layer remains only on the first silicon epitaxial layer. A third oxide layer is thermally grown on entire resultant surfaces and then blanket-etched to remain only on sidewalls of the first silicon epitaxial layer. A second silicon epitaxial layer is grown on the exposed substrate between the first active regions, thus forming second active regions. The second oxide layer remaining on the first silicon epitaxial layer is removed. The first and second active regions are separated and electrically isolated by the third oxide layer.

Abstract: A hetero-junction bipolar transistor that satisfies high resistance required to avoid a potential breakdown includes: an n-type sub-collector layer 110 that is made of GaAs; an n-type first collector 121 that is made of a semiconductor material with a smaller avalanche coefficient than that of the sub-collector 110 and is formed on the sub-collector layer 110; a second collector layer 132 that is made of n-type or i-type GaAs with lower dopant concentration than that of the sub-collector layer 110 and is formed on the first collector layer 121; a p-type base layer 133 that is made of GaAs and is formed on the second collector layer 132; and emitter layer 134 that is made of a semiconductor material with a larger band gap than that of the base layer 133 and is formed on the base layer 133.

Abstract: The present invention provides a method for manufacturing a semiconductor elemental device wherein a first gate oxide film and a second gate oxide film thicker than the first gate oxide film are formed on a substrate provided with a device forming region comprised of silicon, comprising the steps of implanting an element for promoting a forming speed of each gate oxide film into a region for forming the second gate oxide film of the substrate; and simultaneously forming the first gate oxide film and the second gate oxide film by a thermal oxidation method, wherein in the element implanting step, the element is implanted in space of a depth equal to half the thickness of the second gate oxide film placed in predetermination of its formation from the surface of the substrate in such a manner that with the peak of a concentration distribution of the element as the center, a concentration distribution in which both sides of the peak is given twice as large as a standard deviation of the concentration distribution

Abstract: An n-type buffer layer composed of n-type GaN, an n-type cladding layer composed of n-type AlGaN, an n-type optical confinement layer composed of n-type GaN, a single quantum well active layer composed of undoped GaInN, a p-type optical confinement layer composed of p-type GaN, a p-type cladding layer composed of p-type AlGaN, and a p-type contact layer composed of p-type GaN are formed on a substrate composed of sapphire. A current blocking layer formed in an upper portion of the p-type cladding layer and on both sides of the p-type contact layer to define a ridge portion is composed of a dielectric material obtained by replacing some of nitrogen atoms composing a Group III–V nitride semiconductor with oxygen atoms.