Abstract: An alternator and starter tester system having a starter current zero test. The current is measured before and after a solenoid of a starter motor is energized and deenergized to determine if the starter motor should be failed. This allows the operator to quickly determine if the starter motor is stuck on during normal starter motor testing.

Abstract: A method includes installing a device under test (DUT) into each of a plurality of burn-in boards. The method further includes docking each of the burn-in boards to a respective docking location, each of the burn-in boards with a single respective DUT installed therein. The method further includes subjecting the DUTs to a self-heating burn-in procedure while the burn-in boards are docked to the docking locations. Other embodiments are described and claimed.

Abstract: A system for testing a liquid crystal display (LCD) driver includes multiple test boards, each which includes multiple channels that correspond to data channels of fee LCD driver, a device interface board that acts as an interface between the multiple test boards and the LCD driver, a computing device configured to communicate with the multiple test boards, and one or more communications buses over which the computing device communicates with the multiple test boards. Each of the multiple test boards receives partial test data from data channels of the LCD driver, and processes the partial test data to obtain a partial result; and each of the multiple test boards shares a partial result determined from corresponding partial test data with one or more others of the multiple test boards.

Abstract: A universal insert for carrying a BGA package under test primarily comprises a meshed base, at least a latch, and a plurality of lift pins. The meshed base has a component cavity, a mounting surface and a plurality of aligning ball holes in the component cavity where the aligning ball holes are arranged in an array with equal pitch. The latch is disposed inside the meshed base to firmly hold BGA package under test. The lift pins are flexibly extended from the peripheries of the mounting surface of the meshed base. During probe testing, the component cavity accommodates the BGA package inside, at least some of the aligning ball holes are one-on-one aligned to a plurality of solder balls of the BGA package so that the solder balls are exposed from the corresponding aligning ball holes on the mounting surface.

Abstract: A method of forming a planar CMOS transistor divides the step of forming the gate layer into a first step of patterning a resist layer with a first portion of the gate layer pattern and then etching the polysilicon with the pattern of the gates. A second step patterns a second resist layer with the image of the gate pads and local interconnect and then etching the polysilicon with the pattern of the gate pads and local interconnect, thereby reducing the number of diffraction and other cross-talk from different exposed areas.

Abstract: A carrier module that is able to adapt non-standard instrument cards to the architecture of a test system is disclosed. Instrument cards based on non-standard architectures may be combined on a single carrier module. The carrier module is then plugged into the test head of the test system. The carrier module provides circuitry, contained on a plug-in sub-module called an Application Interface Adapter (AIA), to interface between the instrument cards and the test head interface connector. Additionally, the AIA may also provide access from the instrument cards to ATE system calibration circuitry. The carrier module uses the standard data bus of the test system for housekeeping and control functions. A second bus provides the bus for the non-standard instrument cards. Software drivers provided with the instrument cards are encapsulated with an appropriate wrapper so that the cards run seamlessly in the software environment of the test system.

Abstract: A system, apparatus, and method for analyzing photon emission data to discriminate between photons emitted by transistors and photons emitted by background sources. The analysis involves spatial and/or temporal correlation of photon emissions. After correlation, the analysis may further involve obtaining a likelihood that the correlated photons were emitted by a transistor. After correlation, the analysis may also further involve assigning a weight to individual photon emissions as a function of the correlation. The weight, in some instances, reflecting a likelihood that the photons were emitted by a transistor. The analysis may further involve automatically identifying transistors in a photon emission image.

Abstract: A test system includes a communications channel that terminals in a probe, which contacts an input terminal of an electronic device to be tested. A resistor is connected between the communications channel near the probe and ground. The resistor reduces the input resistance of the terminal and thereby reduces the rise and fall times of the input terminal. The channel may be terminated in a branch having multiple paths in which each path is terminated with a probe for contacting a terminal on electronic devices to be tested. Isolation resistors are included in the branches to prevent a fault at one input terminal from propagating to the other input terminals. A shunt resistor is provided in each branch, which reduces the input resistance of the terminal and thereby reduces the rise and fall times of the input terminal. The shunt resistor may also be sized to reduce, minimize, or eliminate signal reflections back up the channel.

Abstract: An apparatus for providing current to a device under test includes a first parametric measurement unit configured to provide current to the device, and a second parametric measurement unit configured to provide current to the device. The current from the second parametric measurement unit augments the current from the first parametric measurement unit at the device.

Abstract: A Printed Circuit Board (PCB) test fixture includes flex sensors for monitoring the flex (or distortion) of the PCB during testing. The PCB is positioned above irregular array of test probes. The test probes are aligned with electrical test points on the PCB. The PCB is then pressed downward against the test probes by an irregular array of pushers. The positions of the pushers are generally specified by a PCB manufacturer to avoid PCB elements and the positions of the test probes are generally specified by the PCB manufacturer to obtain desired signals.

Abstract: A transmission Line Pulse (TLP) device calibration method wherein the TLP device includes a pulse generator for generating a pulse, a cable having an input terminal coupled to said pulse generator, an output terminal, and at least one ground return terminal, for coupling said pulse to a device under test (DUT) when it is connected to said output terminal, and a sensor for sensing the voltage and current at a selected point in said cable to measure the pulsed voltage and current of the DUT as the pulses travel in the cable to and from the DUT.

Abstract: Characteristics of a power MOSFET gate charge test waveform are evaluated to yield a highly reliable and uniform testing methodology that replaces the inconsistent and inefficient dv/dt immunity testing currently performed. The invention utilizes the ratio of QGD over QGS1 to replace traditional dv/dt immunity testing in order to perform binning and sorting the devices. The ratio of QGD over QGS1 has proven to be a very reliable substitute for standard dv/dt immunity tests, and a very accurate predictor of a power MOSFET's suitability for a specified purpose. Because the gate charge parameters are relatively easily measured with high accuracy, and independent of test set-up or tester, reliability is far greater than previous methods and improved efficient results. Additional ratios of charge parameters enhance the performance of the testing methodology of the present invention.

Abstract: A current sensor includes an integrator for providing an output signal, responsive to a detected current, and a reset circuit. The reset circuit, responsive to a control signal, resets the integrator for a time period shorter than an assertion time of the supplied control signal.

Abstract: A power supply voltage detecting circuit includes a voltage regulating circuit, a comparative circuit, a timer circuit, and a display circuit. The voltage regulating circuit provides a stable reference voltage to the comparative circuit. The comparative circuit compares the reference voltage with the voltage from the power supply. The comparative circuit is electrically connected to the display circuit via the timer circuit. The display circuit includes light emitting diodes for revealing a status of the voltage from the power supply. The timer circuit causes the display circuit to keep a light on when there has been an occurrence of abnormal voltage from the power supply until an operator resets it.

Abstract: An apparatus and method are provided which preferably combines temperature sensing and prediction for more accurate temperature control of integrated circuits. An IC temperature sensing and prediction device includes a current sensing device that measures current passing through an IC, and a temperature control apparatus that measures a surface temperature of the IC. The device further includes an electronic controller that calculates the power consumed by the IC according to the measured current and adjusts the temperature of a heater or cooler responsive to the measured surface temperature and power consumption.

Abstract: A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.

Abstract: A playground play feature comprising a track having a glide board thereon, such that a user may run and jump onto the glide board and propel the board along the length of the track. The glide board further can comprise a rubber, or similar material, covered board having wheels, the wheels designed to fit within angled side rails, so that the glide board is held onto the track along the entire length of the track. The track further comprises shock absorbing end caps so as to more controllably stop the glide board as it nears the end of the track.

Abstract: A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within the substrate results in a compliant deflection orthogonal to the plane of the substrate. The contact pin assembly is formed by generally thinning the substrate around the contact pin location and then specifically thinning the substrate immediately around the contact pin location for forming a void. The contact pin is compliantly coupled, in one embodiment by compliant coupling material, and in another embodiment by compliantly flexible portions of the substrate.

Abstract: A method of determining the time to failure of parallel electro migration test structures is described. The method generally includes the steps of: measuring the resistance of the complete structure; calculating the resistance of the n individual parallel structures from the measured resistance; calculating the resistance of the complete structure after the failure of m individual parallel structures, for m=1 to n; and recording the time of failure for each m as the time when the resistance is approximately the value predicted for m fails.

Abstract: Methods and apparatus are provided for performing loopback testing of integrated circuits (“ICs”). In an embodiment of the invention, an IC can be tested on an undiced wafer by coupling a wireless transmitter of the IC to a wireless receiver of the IC. Core circuitry of the IC can be controlled to cause the transmitter to send at least one signal to the receiver. Upon receipt of the at least one signal, the receiver can send a signal to the core circuitry, which can determine, and possibly record, whether the transmission and receipt were successful. The invention advantageously facilitates efficient testing of unpackaged ICs at the wafer level.