Patents Examined by Ha Tran Nguyen
  • Patent number: 7388363
    Abstract: A detector circuit is to be used for measuring current by means of substantially identically wound ring core transformers, in which magnetomotive forces are induced by a main current. The magnetomotive forces are counteracted by magnetomotive forces induced by a compensating current. Two of the ring core transformers (2, 3) are magnetized in antiphase by means of a modulation signal. The detector circuit includes optionally a synchronous rectifier for providing an adjusting signal for the compensating current. According to the invention means are provided for compensating for possible differences between the two ring core transformers for the modulation signal. These means include a cornmon winding surrounding the two ring cores (2, 3), said common winding detecting a possible error signal used in a negative feedback loop which automatically seeks to establish an equilibrium.
    Type: Grant
    Filed: November 26, 2004
    Date of Patent: June 17, 2008
    Assignee: Danfysik A/S
    Inventor: Hans Erik Jørgensen
  • Patent number: 7388397
    Abstract: A testing method for an array substrate is disclosed which includes a first measuring step of operating a line electrode driver circuit 15 and a row electrode driver circuit 16 like in a normal display mode while implementing writing in/reading out of a test video signal to and from supplemental capacitors 13, and a second measuring step of implementing writing in/reading out of the test video signals to and from a video bus 163 while rendering TFTs 11 of a pixel section 18 and analog switches 162 of the row electrode driver circuit 16 to be held turned off. Obtaining a difference between a measured result of the first measuring step and a measured result of the second measuring step allows only a pixel component and a row electrode component with no driver component to be derived, whereupon discrimination is implemented for the presence of or the absence of electric defects in the pixel section.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: June 17, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoru Tomita
  • Patent number: 7388364
    Abstract: A device for covering the peak load of an electrical consumer (VB) that is connected to an alternating current terminal of a public electricity network (ENT). A power inverter (WR) is fed from a direct current accumulator (BAT) and is connected in parallel at the output thereof to the electricity supply (EB) of the consumer (VB). A measuring device (Z1, Z2) is connected in the connection circuit (EN) of the consumer and a control device (STE). With the aid of the measuring device (Z1, Z2), the control device monitors the energy consumption of the consumer (VB), estimates from it a consumption quantity of electrical energy (E*(T)) up to the end (T) of a given time interval, for example via linear extrapolation, and in the event that the prognosis value obtained in this way exceeds a given threshold value (Emax), puts the power inverter (WR) in operation in order to support the supply of the consumer.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: June 17, 2008
    Assignee: Siemens AG Osterreich
    Inventors: Harald Schweigert, Wilhelm Appel
  • Patent number: 7388393
    Abstract: A semiconductor test apparatus is provided that has a function for picking a device as a non-defective device with a limited function (i.e., class B device) even if that device includes one or more defective cells satisfying a predetermined condition. In order to achieve this, the semiconductor test apparatus for classifying devices under test (DUTs) into non-defective devices or defective devices, wherein a DUT including one or more defective cells satisfying a predetermined condition that is acceptable in a specific application is a specifically used DUT (class B device), includes: a specific application classifying means for determining for each of the DUTs whether or not one or more defective cells satisfy the predetermined condition that is acceptable, thereby picking the specifically used DUTs.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: June 17, 2008
    Assignee: Advantest Corporation
    Inventor: Kazuhiro Yamamoto
  • Patent number: 7388396
    Abstract: A strip test method includes the following steps. First, an assembly strip is provided, wherein the assembly strip includes a plurality of semiconductor devices, each having a plurality of leads. A test socket and a base are provided, wherein the test socket has a plurality of probe sets. The assembly strip is loaded to the base. The probe sets electrically contacts the leads of the semiconductor devices simultaneously and respectively so as to process an electrical test. When one of the semiconductor devices is failed in the electrical test, one of the base and the test socket are relatively moved in such a manner that the failed one of the semiconductor devices is corresponding to one of the probe sets which is successful in the electrical test and is the nearest to the failed one of semiconductor device. Finally, the successful and nearest one of probe sets simultaneously and electrically contacts the leads of the failed one of the semiconductor devices so as to process another electrical test again.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: June 17, 2008
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Hsin-Chieh Lu, Chao-Hsiung Hwu
  • Patent number: 7388390
    Abstract: A testing apparatus is described with a housing, a power source, a carrier assembly, and a backbone connecting the carrier assembly to the power source. A resource board is disposed on the carrier assembly and is connected thereto, thereby receiving power from the power source through the carrier assembly. The resource board is adapted to perform a test on a device under test and to generate data reflecting results of the test on the device under test. A test pin assembly is disposed at one end of the resource board and is connectable with a loadboard. A controller operatively connects to the power supply, the carrier assembly, and the resource board. The controller is adapted to communicate with the resource board to execute instructions to test the device under test. The controller also receives the result data from the resource board, permitting analysis of the device under test.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: June 17, 2008
    Assignee: Telco Testing Systems LLC
    Inventors: Roger Brueckner, Michael Costello, James Hopkins, Rudy Sterbenz
  • Patent number: 7388394
    Abstract: A method of testing for misregistration in a multiple layer printed circuit board includes providing an electrical test pattern on one or more layers of the board, testing for an electrical signal between the test pattern and a test reference, and determining layer-to-layer misregistration based on the results of the testing. A method of manufacturing a multiple layer board that is configured to facilitate non-destructive testing of layer-to-layer misregistration includes forming an electrical test pattern on a first layer and forming a corresponding electrical test reference on a second layer. Then, a connecting pathway is formed between the test reference and the test pattern, including the first and second layers, with testing for an electrical signal between the test reference and the test pattern determining layer-to-layer misregistration of the first layer with respect to the second layer.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: June 17, 2008
    Assignee: Cardiac Pacemakers, Inc.
    Inventors: Anthony A. Primavera, Orrin P. Lorenz, Howard L. Bentley
  • Patent number: 7385413
    Abstract: A method of electrically inspecting semiconductor display devices, which is capable of inspecting whether a signal is normally input to the pixels and whether an electric charge is normally held by the holding capacitors without using the video signal line as a passage for reading the electric charge and without separately providing an inspection-dedicated circuit. Power source lines which are used as passages for supplying the power source voltage are used as passages for reading the electric charge. Namely, the power source lines that can be connected to the signal lines are used as passages for inputting an inspection signal to the holding capacitors in the pixels and for reading the electric charge from the holding capacitors in the pixels.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: June 10, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Keisuke Miyagawa, Mitsuaki Osame
  • Patent number: 7385412
    Abstract: Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate having a front side, a backside, and a plurality of microelectronic dies. The individual dies include an integrated circuit and a plurality of contact pads at the backside of the substrate operatively coupled to the integrated circuit. The method includes contacting individual contact pads with corresponding pins of a probe card. The method further includes testing the dies. In another embodiment, the individual dies can further comprise an image sensor at the front side of the substrate and operatively coupled to the integrated circuit. The image sensors are illuminated while the dies are tested.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: June 10, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, William M. Hiatt, Alan G. Wood, Charles M. Watkins, Kyle K. Kirby
  • Patent number: 7385411
    Abstract: A probe card apparatus is configured to have a desired overall amount of compliance. The compliance of the probes of the probe card apparatus is determined, and an additional, predetermined amount of compliance is designed into the probe card apparatus so that the sum of the additional compliance and the compliance of the probes total the overall desired compliance of the probe card apparatus.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: June 10, 2008
    Assignee: FormFactor, Inc.
    Inventor: Benjamin N. Eldridge
  • Patent number: 7382146
    Abstract: Intends to provide semiconductor testing apparatus that can reduce effort to adjust generating timing of a clock signal to be extracted from data or a time required in adjustment. It includes a timing comparator 154 for receiving data outputted from a DUT 200; a clock generating circuit 120 for generating a clock signal synchronized with data outputted from the DUT 200; an absolute amount of delay calculating unit for calculating a signal propagating time corresponding to a difference between a first signal line from the DUT 200 to the timing comparator 154 and a second signal line to the clock generating circuit 120 as an absolute amount of delay; and an amount of delay setting unit for setting the amount of delay under a period of the clock signal according to a frequency or a period of the clock signal generated by the clock generating circuit 120 and ordering adjustment of the clock signal generating timing by the clock generating circuit 120.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: June 3, 2008
    Assignee: Advantest Corporation
    Inventor: Toshiyuki Negishi
  • Patent number: 7382148
    Abstract: A system for testing a light emitting diode (LED) (20) and connectors thereof. The system includes: a chip (10) having general purpose input output (GPIO) function and a plurality of pins (101), a test fixture (30), a parallel interface (40), and a programmable device (50). The programmable device includes a setting module (501), a pin initializing module (502), a potential controlling module (503), a data capturing module (504), and a comparing module (505). A related method is also provided.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: June 3, 2008
    Assignees: Hong Fu Jin Precision Industry (Shen Zhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: De-Hua Dang, Yi-Ching Weng, Ze-Jun Chen
  • Patent number: 7382145
    Abstract: With a docking device for the coupling of a handler or prober to a test head for electronic components, at least one locking unit is provided, which has an axially displaceable ball element clamping sleeve. This ball element clamping sleeve is surrounded by an annular pressure chamber, closing pressure-tight opposite the introduction area of the locking pin and can be moved in an axial direction by means of a ring piston, which can be actuated by a pressure means introduced into the pressure chamber.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: June 3, 2008
    Inventor: Stefan Thurmaier
  • Patent number: 7382142
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: June 3, 2008
    Assignee: NanoNexus, Inc.
    Inventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
  • Patent number: 7375538
    Abstract: Electron beam is irradiated to a wafer in the midst of steps at predetermined intervals by a plurality of times under a condition in which a junction becomes rearward bias and a difference in characteristic of a time period of alleviating charge in the rearward bias is monitored. As a result, charge is alleviated at a location where junction leakage is caused in a time period shorter than that of a normal portion and therefore, a potential difference is produced between the normal portion and a failed portion and is observed in a potential contrast image as a difference in brightness. By consecutively repeating operation of acquiring the image, executing an image processing in real time and storing a position and brightness of the failed portion, the automatic inspection of a designated region can be executed. Information of image, brightness and distribution of the failed portion is preserved and outputted automatically after inspection.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: May 20, 2008
    Assignee: Hitachi, Ltd.
    Inventor: Mari Nozoe
  • Patent number: 7375507
    Abstract: An assembly group for current measurement comprises a conductor plate with three cuts and a measuring element placed on the conductor plate that has a difference sensor formed from two magnetic field sensors. By means of the three cuts a first and a second conductor section are formed in the conductor plate, wherein the current direction in the second conductor section runs opposite to the current direction in the first conductor section. The first magnetic field sensor is located above the first conductor section and the second magnetic field sensor is located above the second conductor section. The magnetic field sensors are sensitive to a magnetic field that runs parallel to the surface of the conductor plate and orthogonal to the current direction in the two conductor sections.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: May 20, 2008
    Assignee: Melexis Technologies SA
    Inventors: Robert Racz, Samuel Huber
  • Patent number: 7374293
    Abstract: An electronic element testing apparatus for use with a number of probes. Each probe has a lower pole and an upper pole. The apparatus includes: a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe; and a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit. The switching circuits are operable to sequentially connect each electronic element to a testing circuit via the upper and lower poles.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: May 20, 2008
    Assignee: Vishay General Semiconductor Inc.
    Inventors: Kuang-Jung Li, Chin-Chen Hsu, Yi-Li Lin, Shyan-I Wu
  • Patent number: 7375540
    Abstract: A method and system for monitoring and compensating the performance of an operational circuit is provided. The system includes one or more integrated circuit chips and a controller. Each integrated circuit chip includes one or more operational circuits, each operational circuit having at least one controllable circuit parameter. Each integrated circuit chip also includes a process monitor module at least partially constructed thereon. The controller is coupled to each process monitor module and to each operational circuit. The controller includes logic for evaluating the performance of an operational circuit based on data obtained from process monitor module and operational circuit related data stored in a memory. Based on the evaluation, the controller determines whether any deviations from desired or optimal performance of the circuit exist. If deviations exist, the controller generates a control signal to initiate adjustments to the operational circuit to compensate for the deviations.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: May 20, 2008
    Assignee: Broadcom Corporation
    Inventors: Lawrence M. Burns, Leonard Dauphinee, Ramon A. Gomez, James Y. C. Chang
  • Patent number: 7375542
    Abstract: Automated test equipment is provided which includes a test head having a tester electronics bricks mounted to a device interface board. In some embodiments, support circuitry is positioned adjacent the tester electronics bricks opposite the DIB. The support circuitry may include power circuitry and/or data bus circuitry, which may be coupled to separate sides, or the same side of the tester electronics brick. A heat transfer apparatus located between the DIB and the support circuitry may be provided for cooling the tester electronics bricks. A tester electronics brick may include multi-chip modules arranged so that the edges generally define interface sides of the tester electronics brick. These sides may include a DIB interface side mounted to the DIB, a data bus interface side, a power interface side, and a heat transfer interface side. Contacts may be located at the edges of the MCMs.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: May 20, 2008
    Assignee: Teradyne, Inc.
    Inventor: Nicholas J. Teneketges
  • Patent number: 7375539
    Abstract: A printed-circuit-board testing device that tests an electronic component disposed on a printed circuit board includes printed-circuit-board-tilt measuring means for measuring tilting of the printed circuit board, measuring means for measuring tilting of an arm having a probe that comes into contact with and tests the electronic component, correcting means for correcting the tilting of the arm on the basis of the tilting of the printed circuit board and the tilting of the arm, inputting means for inputting positional information of the electronic component, arm disposing means for disposing the arm to a predetermined position in accordance with the positional information, and printed-circuit-board testing means for performing testing as a result of protruding the probe from the disposed arm.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: May 20, 2008
    Assignee: Fujitsu Limited
    Inventor: Yasuo Mori