Abstract: A digital power meter apparatus and the method for the same are proposed. The input voltage signal and input current signal through dual channels are processed at a first stage to obtained a first digital signal. The first digital signal is sent to a third low-pass filter. The input voltage signal and input current signal are processed in a second-stage processing through a first low-pass filter, a second low-pass filter and a second logic operation unit to obtain a second digital signal. A third logic operation unit processes the first digital signal and a second digital signal in order to obtain a digital power signal proportion to the product of the two input signals.

Abstract: Auto-recovery wafer testing apparatus and wafer testing method are provided. The wafer testing apparatus includes a main system, a tester and a real-time accessing module. The main system controls the process of the wafer testing. The tester is electrically coupled to the main system for receiving commands from the main system to perform testing on a plurality of chips sequentially and output the testing data correspondingly. The real-time accessing module is electrically coupled to the tester for simultaneously accessing the testing data. In an event when the testing is accidentally interrupted, the tester can produce auto-recovery data according to the testing data saved in the real-time accessing module, and continue testing, based on the auto-recovery data, from the chip being last but incompletely tested. The use of the wafer testing apparatus and method can save testing time and enhance the production efficiency.

Abstract: An electrical test device, in particular for testing wafers, having a contact head, which is associated with the test object and is provided with pin-shaped contact elements that are arrayed to form a contact pin arrangement. An electrical connection apparatus, including contact faces which are in touching contact with ends of the contact elements which face away from the test object. A centering device, which permits only radial play for thermal expansion by sliding guides, for centrally aligning the contact head and the connection apparatus with respect to one another.

Abstract: A power monitoring system comprising a first current sensor suitable to sense first changing electrical current within a first conductor to a first load and a first conductor. A second conductor sensing a first voltage potential provided to the first load. A power monitor superimposes a first signal on the first conductor and first current sensor such that the first signal is sensed on the other of the first conductor and first current sensor. Associating the first voltage potential with first changing electrical current in the power usage calculation of the first load.

Abstract: This invention relates to electrical connectors used with non-invasive toroidal conductivity sensors and calibration thereof. A removable breaking calibration connector is provided for temporary insertion in the electrical circuit to selectively break connection to a sense toroid for zero out calibration in situ while retaining connection to the drive toroid and other peripherals, even when process fluid is flowing in the pipes.

Abstract: An input buffer is presented for buffering an input signal having a voltage magnitude which alternates between a first voltage level and a second voltage level, where the first and second voltage levels may vary over time. In one embodiment, the input buffer includes a first and second detector circuits, an average generator circuit, and a differential amplifier. The first detector circuit receives the input signal and produces a first signal having a magnitude indicative of the first voltage level. The second detector circuit receives the input signal and produces a second signal having a magnitude indicative of the second voltage level. The average generator circuit receives the first and second signals, and uses the magnitudes of the first and second signals to produce a third signal having a magnitude indicative of a third voltage level substantially mid way between the first voltage level and the second voltage level. The third voltage level defines a variable an automatically adjusted “switching point”.

Abstract: An apparatus and method for automatically testing circuit boards, such as computer system boards and the like. The circuit board device under test (DUT) is loaded into an automated test apparatus (tester), which includes a mechanism for automatically connecting test electronics to various DUT circuitry and I/O ports via corresponding connectors on the DUT. A type of DUT is identified, and a corresponding set of tests are performed to verify the operation of the DUT. Appropriate power signals and sequencing are also applied to the DUT, as defined by it type. Data logging is performed to log the results of the testing. The apparatus includes replaceable probe/connector plates that are DUT-type specific and corresponding universal electronics and cabling to enable a variety of different board types to be tested with the same apparatus.

Abstract: A tester device including a tester section which includes a tester, an interconnection board receiving unit fixed on the tester section, and a light source. The interconnection board receiving unit has first and second interconnection boards electrically connected to the tester in the tester section, and a contact section electrically connecting the second interconnection board to an external probe. A cut section for an optical-path is provided in the second interconnection board. The interconnection board receiving unit supports the second interconnection board so as to provide the cut section at the side of the tester section. The light source is moved between an inspection position at which the light source faces the cut section in the second interconnection board and an escape position at which the light source does not face the second interconnection board.

Abstract: An ancillary equipment is provided for testing a semiconductor integrated circuit, by which a plurality of BOST boards serving as measuring units can be set near a device to be measured and tests can be conducted with high accuracy on a number of circuits embedded on a semiconductor integrated circuit such as a system LSI. To achieve an object of performing a go/no go test or a functional/performance characterization in the manufacturing process of the semiconductor integrated circuit, the ancillary equipment includes: a device measuring unit having a measuring section for exchanging a signal with a device or a semiconductor integrated circuit, and an analyzing section for analyzing information from the measuring section using a programmable device; and a control/communication card constituted of a board different from that of the device measuring unit and connected to the device measuring unit to control it, and being capable of performing communication with a general-purpose computer.

Abstract: An apparatus, method, and kit for probing a pattern of points on a first printed circuit board are disclosed. In one exemplary embodiment, the apparatus includes a probe having i) a plurality of compression interconnects to probe the pattern of points on the first printed circuit board, and ii) a plurality of fixed pins that are electrically coupled to the compression interconnects. The fixed pins extend from the probe opposite the compression interconnects. The apparatus further includes a flexible wire interconnect having first and second sets of electrically coupled connectors, the first set of which is coupled to the fixed pins of the probe. A second printed circuit board has at least one first connector that is electrically coupled to at least one second connector. The at least one first connector is coupled to the second set of connectors of the flexible wire interconnect, and the at least one second connector is configured to couple to a test instrument.

Abstract: A method of forming a protective layer over a metal filled semiconductor feature to prevent metal oxidation including providing a semiconductor process wafer comprising an insulating dielectric layer having an opening for forming a semiconductor feature; blanket depositing a metal layer over the opening to substantially fill the opening; and, blanket depositing a protective layer comprising at least one of a oxidation resistant metal and metal nitride over the metal layer.

Abstract: To reduce noise in measurements obtained by probing a device supported on surface of a thermal chuck in a probe station, a conductive member is arranged to intercept current coupling the thermal unit of the chuck to the surface supporting the device. The conductive member is capacitively coupled to the thermal unit but free of direct electrical connection thereto.

Abstract: An apparatus for routing power between a set of power supply taps of an automated tester and power connections on an integrated circuit under test, where the integrated circuit belongs to a family of integrated circuits that have a common power connection layout and different power connection voltage requirements. An interface board having first electrical contacts disposed in the common power connection layout makes electrical connections to the power connections of all integrated circuits belonging to the family of integrated circuits. The first electrical contacts are electrically routed to second electrical contacts disposed in a standardized configuration. A power personality card having third electrical contacts makes electrical connections to the second electrical contacts of the interface board.

Abstract: A terminal block probe for taking electrical current measurements through an isolating terminal block by a multi-meter includes a tip configured as an isolating terminal block pin corresponding to the isolating terminal block pin of the particular isolating terminal block under test. This allows the probe to be releasably held by the terminal block for hands free testing. The probe tip includes two conductors adapted for contact with the isolating pin terminals of the terminal block. The terminal block probe includes a socket that releasably receives a plug of a multi-meter cable. Internal wiring of the probe extends from the socket and connects with the two conductors of the tip. When the plug of the multi-meter cable is received within the socket, the conductors of the tip are in electrical continuity with the wires of the multi-meter cable and thus the multi-meter.

Abstract: A manipulator for supporting heavy as well as lighter test heads in a small footprint includes a body and an interface for supporting a test head from behind. The interface includes a first portion fixedly attached to the body and a second portion fixedly attached to the rear of the test head. The first and second portions of the interface are rotatably coupled together to allow rotation of the test head about its approximate center of mass. Although the weight of the test head is entirely borne from the rear, the test head can still be moved with relatively little applied force, thereby satisfying the requirements for compliant docking.

Abstract: A method for test data-driven detection of outlier semiconductor devices. Some illustrative embodiments may be a method used to test a semiconductor die comprising performing a burn-in test of a plurality of sample semiconductor dies to identify a failure of a defective semiconductor die, correlating variations in a parameter with the failure (the parameter comprising a characteristic associated with the plurality of sample semiconductor dies), defining a parameter constraint associated with the parameter, performing a production test of a production semiconductor die, and identifying the production semiconductor die as an outlier semiconductor die (the outlier semiconductor die passing the production test, but failing to conform to the parameter constraint).

Abstract: The invention relates to a test device for testing an integrated circuit called test circuit, comprising a plurality of housings intended to be tested in a printed circuit called main circuit. The device comprises an insulating membrane of soft material having two opposite surfaces covered by two conductive layers interconnected by via holes and intended to be in contact with the test circuit and the main circuit respectively, under the influence of a pressure exerted during the test between the test circuit and the main circuit pressing the test device. Protrusions are arranged on at least one of the two layers in a predefined pattern as a function of said pins, tabs, pads etc. of the test circuit so as to ensure a contact quality between said layer and the circuit (to be tested or the main circuit) having contact with said layer under the influence of said pressing action.

Abstract: The disclosure relates to a semiconductor device testing apparatus, a semiconductor device testing system, and a semiconductor device testing method, in particular a method for measuring or trimming, respectively, the impedance of driver devices provided in a semiconductor device, wherein a device, in particular a driver device, comprising each a pull-up circuit and a pull-down circuit is used, and wherein the method includes: joint activating of both the pull-up circuit and the pull-down circuit; and determining a first current flowing through the pull-up circuit or the pull-down circuit, respectively, with jointly activated pull-up and pull-down circuits.

Abstract: One embodiment of the present invention provides a system that performs voltage sampling over an extended voltage range on a semiconductor chip. During operation, the system receives an input voltage at a node within the semiconductor chip. The system samples the input voltage through a first sampling pathway using NMOS pass gates, which latch the input voltage to produce a first output signal. This first output signal tracks the input voltage from ground up to a cut-off voltage for the nMOS pass gates. The system also samples the input voltage through a second sampling pathway using nMOS pass gates, which latch the input voltage to produce a second output signal. Prior to the NMOS pass gates along the second sampling pathway, the input voltage passes through a source-follower gate, which translates the input voltage down, so that the second output signal tracks the input voltage from a turn-on voltage of the source-follower gate up to Vdd.

Abstract: An integrated circuit (IC) temperature sensing device includes a temperature sensor positioned within a conductive temperature sensor housing and a thermal insulator surrounding the conductive temperature sensor housing. The sensor housing and thermal insulator are positioned within an IC temperature control block that heats or cools the IC. The temperature sensor housing comes into thermal contact with an IC undergoing burning-in, testing or programming. The temperature sensor housing provides a short thermal path between the IC under test and the temperature sensor. The thermal insulator thermally isolates the temperature sensor from the temperature control block so that the temperature sensor predominantly measures the temperature of the IC.