Abstract: A test methodology which provides that test structures, such as transistors, are arranged in a plurality of rows. A logic circuit controls which row is to be measured. An incrementer receives a triggering signal and functions as an address adder. Each time the triggering signal rises from 0 to 1, the output of the incrementer increases by 1. The output of the incrementer serves as the address input into a decoder. The decoder is connected to the rows of test structures. Preferably, each test structure contains a control circuit which is controlled by this signal (i.e., the output of the decoder). If the test structures are transistors, bias to each of the transistors can be applied separately with a common gate, source and well, and measurement can be done with a separate drain node.

Abstract: A contact probe is fabricated by forming a resin mold with a cavity on a substrate having conductivity, and filling the cavity with metal through electroforming. The metal includes a cobalt-tungsten alloy. Alternatively, a cobalt-molybdenum alloy may be used instead of the cobalt-tungsten alloy. Alternatively, a contact probe can be made from nickel, cobalt or copper, and have a coat film of cobalt-tungsten alloy or cobalt-molybdenum alloy formed thereon to increase the abrasion resistance. A nickel-molybdenum alloy can be used instead of the cobalt-tungsten alloy or cobalt-molybdenum alloy.

Abstract: In one example, a wafer level burn-in system includes a first electrode plate for providing electrical contact simultaneously to contacts of a group of semiconductor devices borne by a semiconductor wafer on a device surface of the semiconductor wafer. A second electrode plate is employed for providing electrical contact to a substrate surface of the semiconductor wafer. Finally, an electrical power generator is employed for providing electrical power to the group of semiconductor devices through the contacts and the substrate of the semiconductor wafer through the first and second electrode plates.

Abstract: Various methods and systems for determining one or more properties of a specimen are provided. One system for determining a property of a specimen is configured to illuminate a specimen with different wavelengths of light substantially simultaneously. The different wavelengths of light are modulated at substantially the same frequency. The system is also configured to perform at least two measurements on the specimen. A minority carrier diffusion length of the specimen may be determined from the measurements and absorption coefficients of the specimen at the different wavelengths. Another system for detecting defects on a specimen is configured to deposit a charge at multiple locations on an upper surface of the specimen. This system is also configured to measure a vibration of a probe at the multiple locations. Defects may be detected on the specimen using a two-dimensional map of the specimen generated from the measured surface voltages.

Abstract: Noise reduction for application of structural test patterns to a Device Under Test (DUT) is accomplished with a capacitor “booster” bypass network on the probe card in which the capacitors are charged to a much higher voltage Vboost than the DUT power supply voltage VDD. Charging the capacitors to a voltage N×VDD allows the buster network to store N times the charge of a conventionally configured capacitance network, and effectively provides N times the capacitance of the original network in the same physical space.

Abstract: A system for testing with an automated test equipment (ATE). The ATE includes a tester, an interface board connected to the tester, a first socket and a second socket of the interface board, a first manipulator arm connected to the tester, and a second manipulator arm connected to the tester. The first socket and the second socket are parallel-wired to the tester. The ATE also includes a switch connected to the tester and the interface board. The switch selectively effects communicative connection of the tester to either of the first socket or the second socket at each instant. During testing via one of the sockets, one of the manipulator arms moves post-test devices and replaces next devices for testing in the other of the sockets. After testing via one of the sockets is completed, the switch immediately connects the other socket and testing of next devices commences and continues for those devices.

Abstract: An integrated circuit burn-in test system includes an integrated circuit and a tester. The integrated circuit includes operating circuitry, a heater for heating the operating circuitry, and burn-in test circuitry for testing the operating circuitry while being heated. A package surrounds the operating circuitry, the heater and the burn-in test circuitry. The burn-in test circuitry causes the operating circuitry to operate and generate data related thereto. The tester receives data from the burn-in test circuitry. The heater may be configured within the package to heat at least one predetermined portion of the operating circuitry.

Abstract: A control unit of a wafer prober for implementing wafer examination, using a probe card including a multiple number of probes, executes a multiple number of measuring operations by bringing the probes of the probe card into contact with bonding pads formed on a wafer and by measuring the electric characteristics between predetermined pads of the bonding pads, each of the measuring operations being implemented after varying the relative position between the probe card and the wafer, in directions parallel to the face of the wafer. The control unit, upon execution of each of the measuring operations, implements the measuring operation after adjusting the relative position between the probe card and the wafer so that the contact position of each probe of the probes against each pad of the bonding pads is separated from all the positions at which the probes have already touched that pad of the bonding pads for a predetermined number of different times.

Abstract: An isolation resistor is incorporated into the plunger of a probe tip spring pin by, for example, doping a ceramic that is used to form the plunger, or forming the plunger of first and second electrically coupled materials, at least a first of which has a resistivity sufficient to serve as an isolation resistor. Alternately, an isolation resistor is embedded in a printed circuit board trace that is used to couple either an upper or lower blind plated hole to a via. A probe tip spring pin is then inserted into the upper blind plated hole.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: A thin film transistor liquid crystal display (TFT-LCD) source driver for implementing a self burn-in test and a self burn-in test method are provided. The TFT-LCD source driver includes a self burn-in signal generator that generates a self burn-in signal and a burn-in load signal, a burn-in data generator that generates a burn-in data signal and a burn-in polarity control signal in response to the self burn-in signal and a clock signal. The TFT-LCD source driver also includes first and second switching units. The first switching unit transmits the burn-in load signal as an internal load signal, transmits the burn-in data signal as an internal digital data signal, and transmits the burn-in polarity control signal as an internal polarity control signal, in response to activation of the self burn-in signal. The second switching unit transmits outputs of output drivers to all channels of the TFT-LCD source driver in response to the internal load signal.

Abstract: BUR920020148US13 A method of tuning an integrated circuit on an integrated circuit chip including: performing a drain current at saturation measurement of one or more test field effect transistors on the integrated circuit chip; selectively programming fuses of a bank of fuses on the integrated circuit chip based on the drain current at saturation measurement; and tuning an output of the integrated circuit based on a pattern of blown and un-blown fuses in the bank of fuses.

Abstract: The invention, which relates to a wafer lifting device having a lifting platform arranged under a wafer receptacle, which lifting platform can be moved in the vertical direction and at least three pins which can be moved in through holes in the wafer receptacle. The pins are separately guided in the through holes. A pin is guided and held such that it can be moved longitudinally, and the pin guide is fixedly connected to the wafer receptacle.

Abstract: The invention relates to a test device for testing digital semiconductor circuits at wafer level having a probe card which sends/receives digital test signals to/from a test head and distributes signal channels, carrying test signals, to the respective location on the wafer via an interposer. The interposer has a printed circuit board with contact pins on both sides, and a needle or contact stud card. Additionally, all signal channels in the test device or signal channels which carry time-critical test signals in the test device contain a respective signal amplifier, the signal amplifiers preferably being digital signal amplifiers which are mounted on the printed circuit board of the interposer.

Abstract: The present invention is a method of measuring capacitance of micro structures in an integrated circuit wherein the micro structure includes a first terminal and a second terminal separated by an insulator and at least a third terminal separated from the first terminal by an insulator. The method comprises applying biasing voltage to the second terminal and applying the same potential to the first and third terminals. An electrical characteristic between the first and second terminals are measured to determined the capacitance between the first and second terminals.

Abstract: An accessible optical path to a lower surface of a heatable device under test is provided by a thermal optical chuck comprising a transparent resistor deposited on transparent plate arranged to supporting the device in a probe station.

Abstract: An inspecting apparatus for semiconductor devices including: a match plate; a contact module combined with the match plate, and the match plate including a radiation unit radiating heat from the semiconductor devices to the outside, and a test unit contacting leads of the semiconductor; an insert module installed on a bottom of the contact module, and having a semiconductor device accommodator to accommodate the semiconductor device; and an auxiliary radiation member installed on a bottom of the insert module, and radiating the heat from the semiconductor device to the outside. Accordingly, the inspecting apparatus for semiconductor device according to the present invention performs testing at a constant temperature regardless of heat from the semiconductors by radiating the heat from the semiconductors immediately and efficiently, thereby producing more accurate test results.

Abstract: Where double sided circuit boards are utilized, having components on both sides, cooling is easily achieved by utilizing an appropriate thermal bonding agent which is both thermally conductive and electrically insulating. The thermal bonding agent is coupled to the circuit board in a manner which surrounds and encapsulates components on one side of the circuit board. Attached to the other side of the thermal bonding material is a heat sink, or other heat management device. By using this configuration, heat is easily transmitted from the electrical components to the heat sink, while not creating any electrical interference or shorts for circuit components in contact with the thermal bonding material.

Abstract: A polish method for planarization is disclosed. The method uses a combination of a traditional oxide CMP and HSP-CMP (High Selectivity and Planarization) with a fix abrasive pad to meet the requirements of the CMP process for a device feature dimension under 0.18 micron even to 0.09 micron. By using a first polish step with a conventional polish pad and an oxide polish slurry, the non-uniformity of the over-fill thickness of the STI dielectric layer can be firstly removed and a much more smooth and uniform topography favorable for the HSP-CMP process the fix abrasive polishing pad can be obtained. Then the HSP-CMP process with the fix abrasive polishing pad can be performed to provide a planarized surface with accurate dimension control.

Abstract: The invention provides tester load board shields (10, 40) for attachment to tester load boards. The shields (10, 40) of the invention protect from physical damage and electromagnetic interference. A preferred embodiment of a tester load board shield (10) of the invention is disclosed in which a disc (12) and outer rim (14) of conductive metal such as aluminum or aluminum alloy are configured to accept a tester load board. The tester load board shield (10) has holes (18) to align with a selected tester load board for attachment of the shield (10) thereto. Stanchions (22) are provided to facilitate attachment of the Loadboard with shield (10) to automatic test equipment known in the arts while a tester load board, also familiar in the arts, is fastened to the shield (10). Another embodiment of a tester load board shield (40) is disclosed in the shape of annulus (42) configured to contain a tester load board within an outer rim (44), planar surface (46), and inner rim (50).