Patents Examined by Ha Tran Nguyen
  • Patent number: 7235995
    Abstract: A test apparatus that tests a device under test, including a main memory having an expectation pattern storing region storing an expectation pattern sequence to be sequentially compared with output patterns sequentially output from a terminal of the device; a test pattern outputting unit for sequentially inputting a plurality of test patterns into the device; a capture unit for sequentially acquiring the output patterns into an output pattern storing region on the main memory; a memory reading unit for reading an output pattern sequence consisting of the plurality of acquired output patterns and the expectation pattern sequence from the main memory when the acquisition process acquiring the output patterns into the output pattern storing region has been terminated; and an expectation comparing unit for comparing the read expectation pattern sequence and the output pattern sequence.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: June 26, 2007
    Assignee: Advantest Corporation
    Inventors: Tomoyuki Sugaya, Hiroyasu Nakayama
  • Patent number: 7233157
    Abstract: A test board for a high-frequency system level test: The test board includes a main board having through holes filled with a conductive material. These holes may be located at a portion of the main board from which an existing module socket has been removed. An interface board has surface mounted device (SMD) pads on front and rear surfaces. The SMD pads on the front surface of the interface board are connected with the SMD pads on the rear surface thereof through cross connection wiring within the interface board for a pin swap. The through holes of the main board are connected with the SMD pads on the rear surface of the interface board via iron cores fixed at a guide. A test module socket is mounted on surfaces of the SMD pads on the front surface of the interface board.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: June 19, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Kuk Lee, Young-Man Ahn, Seung-Man Shin, Jong-Cheol Seo
  • Patent number: 7233159
    Abstract: Apparatuses and methods for testing electronic components, such as printed circuit boards, in an ergonomic manner are disclosed. An electronic component testing apparatus comprises a base, a test chamber rotatably mounted to the base, and a heating and cooling unit coupled to the test chamber. The test chamber further includes a chassis defining an enclosure having an opening and at least one test slot accessible through the opening for facilitating operative coupling of an electronic component to the test chamber for testing of the electronic component.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: June 19, 2007
    Assignee: EMC Corporation
    Inventor: Joseph Peter Allgeyer
  • Patent number: 7233156
    Abstract: A plurality of probes such as a signal probe (3) and a power supply probe (4) are provided into a metal block (1) so as to penetrate. Each of the probes has a movable pin (11). A tip of the movable pin is projecting from one surface of the metal block (1). And a projection length of the tip is variable. A DUT 20 is pressed onto the surface of the metal block (1) to contact between electrode terminals (21 to 24) and tips of the probes to test characteristics of the DUT. At least one of the probes is capacity loaded probe having a capacitor by providing a dielectric layer and a metal film to peripheral of the probe. As a result, noise can be removed reliably. Additionally, when the capacity loaded probe is used as the power supply probe, a voltage drop is reduced at the power supply terminal in a case of change of the output.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: June 19, 2007
    Assignee: Yokowo Co., Ltd.
    Inventors: Wasuke Yanagisawa, Makoto Nakakoji, Ryo Horie, Takuto Yoshida
  • Patent number: 7230414
    Abstract: A current sensor that includes a pair of segments. Each of the segments includes magnetically permeable cores that can be joined together. A winding is used to substantially encircle one of the cores.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: June 12, 2007
    Assignee: Veris Industries, LLC
    Inventor: David A. Bruno
  • Patent number: 7230442
    Abstract: The invention involves a semi-conductor component testing process, and a system for testing semi-conductor components, in which a central computer device, in particular a central test apparatus is provided, with which test result data obtained from at least two separate tests is jointly evaluated, in particular by means of an appropriate pattern recognition process, which incorporates the test result data obtained from the separate tests into the analysis.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: June 12, 2007
    Assignee: Infineon Technologies AG
    Inventors: Georg Müller, Michael Kund
  • Patent number: 7230436
    Abstract: The present invention relates to a laser beam inspection apparatus for inspecting a defect on a sample such as semiconductor integrated circuits by using a laser beam. The laser beam inspection apparatus irradiates a laser beam to a sample supplied with a constant current or applied by a constant voltage, and then detects indirectly a change in current or a change in electric field corresponding to a change in the value of resistance developed by scanning the laser beam along the surface of the sample. For example, the change in current is conducted indirectly in such a manner that a magnetic field detecting apparatus detects the change in the magnetic field caused by a current flowing the power supply line provided between a constant voltage source and a sample, and whereby it becomes possible to specify the defective area of the sample based on the detection of the change in the magnetic field.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: June 12, 2007
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hirotoshi Terada, Hiroyoshi Suzuki, Toshimichi Ishizuka
  • Patent number: 7230439
    Abstract: A system and method for detecting and monitoring wafer probe stability including the steps of, probing each die on a wafer, and for each die determining whether the result of the probe is a pass or a fail. If the result of a probe is a fail, re-probing the die and determining whether the re-probe is a pass or a fail. Once all the dies have been probed determining the rate of die re-probes that lead to passes, comparing the rate of passes on re-probes to a pre-determined limit, and if the rate of passes on re-probes is greater than the predetermined limit, assigning the probe status as unstable.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: June 12, 2007
    Assignee: Systems on Silicon Manufacturing Co. Pte. Ltd.
    Inventor: Beng Ghee Tan
  • Patent number: 7230416
    Abstract: An inspecting apparatus (20, 40, 50, 60) for liquid crystal displays includes a base plate (21, 41), a connecting device (200, 400) mounted on the base plate, a working table (25, 45, 55, 65) supported on the connecting device, and an electrical holding device (29) fixed to the working table. The electrical holding device can hold a mains switch (33) and an electrical connector (31) that is used to connect with leads of the LCD. Because the inspecting apparatus includes the electrical holding device for holding the electrical connector, operators can connect leads of the LCD and the electrical connector easily using a single hand. After that, operators can conveniently turn on the mains switch because the mains switch is adjacent to the electrical connector.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: June 12, 2007
    Assignees: Innocome Technology (Shenzhen) Co., Ltd., Innolux Display Corp.
    Inventors: Chung-Sung Huang, Eadle Chen, Xiao-Li Jin
  • Patent number: 7230417
    Abstract: A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: June 12, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ae-Yong Chung, Eun-Seok Lee, Jeong-Ho Bang, Kyeong-Seon Shin, Dae-Gab Chi, Sung-Ok Kim
  • Patent number: 7227374
    Abstract: A liquid crystal display (LCD) inspection apparatus is provided which is capable of preventing detection of defects from being omitted or degraded due to formation of stains in a certain region of an LCD panel in an inspection of the LCD panel.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: June 5, 2007
    Assignee: LG. Philips LCD Co., Ltd.
    Inventors: Dong Woo Kang, Soung Yeoul Eom, Bong Chul Kim, Ki Soub Yang
  • Patent number: 7227364
    Abstract: The embodiments of the present invention enable a new metal diagnosis pattern based on a production test pattern to quickly identify open and short circuits of metal lines which cannot be probed, such as the long lines of a programmable logic device, and to further isolates the fault location for physical failure analysis. According to one aspect of the invention, a circuit locally drives a plurality of metal long line segments to determine whether a defect in a line is a short circuit, or further to identify the location of an open circuit.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: June 5, 2007
    Assignee: Xilinx, Inc.
    Inventors: Yuezhen Fan, David Mark, Eric J Thorne, Zhi-Min Ling
  • Patent number: 7227369
    Abstract: Described are methods of using probes, for making electrical contact to high-density chips or similar electronic devices. Two groups of probes are covered. The first group includes probes that are moved laterally, parallel to the surface of the contact pads of the device under test, after the initial contact has been made. This is to create the desired wipe or scrub. The second group includes probes that operate on the principle of suction cups. When the probe is pushed against the device under test, the probe working tips stretch outwardly and create the desirable wipe or scrub. Described also are the probes themselves that are used for the above methods.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: June 5, 2007
    Inventor: Gabe Cherian
  • Patent number: 7227372
    Abstract: An Electrical Die Sorting (EDS) process system for testing semiconductor chips comprises a probe station, a power supply unit configured in the probe station, and a voltage apparatus for measuring voltages of the power supply. The voltage apparatus comprises a measuring unit connected with voltage check terminals and a common ground terminal of the power supply unit, for measuring voltages between each of the voltage check terminals and the common ground terminal simultaneously; and a plurality of display units electrically connected with the measuring unit, for monitoring voltages of the respective voltage check terminals in real time.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: June 5, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jun-Su Bae
  • Patent number: 7224173
    Abstract: An apparatus and a method for electrically testing a microelectronic product employ an electrical probe tip for electrically stressing a portion of the microelectronic product other than an electrical contact portion of the microelectronic product when electrically testing the microelectronic product. The apparatus and the method provide for more accurate and efficient electrical testing of the microelectronic product.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: May 29, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Hui-Chuan Hung
  • Patent number: 7224160
    Abstract: A RF and pulse bias tee for use with a source measure unit (SMU) includes a SMU source terminal; a SMU measure terminal; an output terminal; a SMU measure terminal pulse/RF block between the SMU measure terminal and the output terminal; a SMU source terminal high frequency block having two end nodes and an intermediate node, the end nodes being connected between the SMU source terminal and the output terminal; a RF input; a pulse/DC block between the RF input and the output terminal; a pulse input; and a DC block between the pulse input and the intermediate node.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: May 29, 2007
    Assignee: Keithley Instruments, Inc.
    Inventor: Alexander N. Pronin
  • Patent number: 7221181
    Abstract: Power measurement and control in transmission systems are affected by changes in load conditions. A method and system are provided for detecting and controlling power levels independent of such load conditions.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: May 22, 2007
    Assignee: Harris Stratex Networks Operating Corporation
    Inventors: Yen-Fang Chao, Cuong Nguyen, Roland Matian
  • Patent number: 7221175
    Abstract: A system for docking a device handler for an electrical device with a test head includes providing a device handler for holding the electrical device, the device handler having a plurality of docking pins. A test head having a plurality of docking modules mounted thereon is provided. The plurality of docking pins is aligned with the plurality of docking modules. The plurality of docking pins is inserted into the plurality of docking modules. The plurality of docking pins is secured in the plurality of docking modules in a docked position to connect the device handler to the test head.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: May 22, 2007
    Assignee: Stats Chippac Ltd.
    Inventor: Ramesh Ramamoorthi
  • Patent number: 7221173
    Abstract: An interface assembly (20) and method for testing a semiconductor wafer prior to performing a flip chip bumping process are provided. The interface assembly includes a flip chip bonding pad (24) having a region (28) for performing the bumping process. A test pad (22) is integrally constructed with the bonding pad and includes a probe region (26) for performing wafer-level testing prior to performing the bumping process. The integral construction of the bonding and testing pads avoids, for example, an introduction of propagation delays to test signals passing therethrough, thereby improving the accuracy and reliability of wafer test results.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: May 22, 2007
    Assignee: Agere Systems, Inc.
    Inventors: Mark Adam Bachman, Daniel Patrick Chesire, Taeho Kook, Sailesh M. Merchant
  • Patent number: 7221146
    Abstract: A probe station with an improved guarding structure.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: May 22, 2007
    Assignee: Cascade Microtech, Inc.
    Inventors: John Dunklee, Greg Norgden, C. Eugene Cowan