Patents Examined by Hai L. Nguyen
  • Patent number: 11967816
    Abstract: An input/output (I/O) interface includes a resistance-to-current (R/I) converter; an internal resistor; first, second, and third current sources; first and second diodes; and a comparator. The R/I converter is coupled to an I/O pin and generates an output current based on an external resistance at the I/O pin during an analog operating mode. The internal resistor is coupled to the I/O pin and to ground. The first current source is coupled to the R/I converter circuit. The first diode is coupled to the R/I converter and to the I/O pin. The second current source is coupled to the R/I converter and the first diode and to ground. The second diode is coupled to the I/O pin and to the third current source. The comparator has inputs coupled to the I/O pin and to a reference voltage, and outputs a control signal indicative of a digital operating mode.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: April 23, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ishaan Kubba, Sreeram Nasum Subramanyam, Shishir Goyal, Deep Banerjee
  • Patent number: 11962273
    Abstract: An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: April 16, 2024
    Assignee: NEC Advanced Networks, Inc.
    Inventors: Mihai Banu, Yiping Feng
  • Patent number: 11961712
    Abstract: This disclosure describes systems, methods, and apparatus for calibrating sensors used by a match network during tuning of power delivery to a plasma processing chamber. The calibration can include self-calibration of two sensors in isolation relative to a self-load, and Relative or Absolute mutual calibration of both sensors used together across a mutual load. The mutual calibration can determine errors between the two sensors after they are each calibrated in isolation, and this additional calibration provides previously unrealized tuning accuracy.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: April 16, 2024
    Assignee: Advanced Energy Industries, Inc.
    Inventor: Frederick Winter
  • Patent number: 11955945
    Abstract: An electronic component capable of obtaining higher attenuation characteristics. The electronic component includes a substrate, a first inductor and a second inductor disposed on a main surface of the substrate, and a transmission line provided on the substrate and connecting the first inductor and the second inductor in series. A first central axis of the first inductor and a second central axis of the second inductor are parallel to a main surface of the substrate and are not located on the same linear line when viewed from a direction orthogonal to the main surface of the substrate. The first inductor and the second inductor are arranged at a distance for magnetic coupling.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: April 9, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Noboru Shiokawa
  • Patent number: 11955979
    Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: April 9, 2024
    Inventors: Reetika K Agarwal, Abbas Komijani, Hongrui Wang
  • Patent number: 11921534
    Abstract: Various aspects relate to a startup circuit for a bandgap reference circuit, wherein a target voltage value is associated with the bandgap reference circuit, the target voltage value being indicative of a startup condition of the bandgap reference circuit that triggers a stable on-state of the bandgap reference circuit, wherein the startup circuit is configured to: provide a startup voltage at the bandgap reference circuit to trigger a start of an operation of the bandgap reference circuit; receive a feedback voltage, wherein the feedback voltage is representative of a startup condition of the bandgap reference circuit; and either increase the startup voltage at the bandgap reference circuit in the case that a voltage value of the feedback voltage is less than the target voltage value, or stop providing the startup voltage at the bandgap reference circuit in the case that the voltage value of the feedback voltage is equal to or greater than the target voltage value.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: March 5, 2024
    Assignee: FERROELECTRIC MEMORY GMBH
    Inventor: Rashid Iqbal
  • Patent number: 11916567
    Abstract: An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. A first capacitor is coupled between the first and second transistors and a second capacitor is coupled between the third and fourth transistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: February 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sai Aditya Krishnaswamy Nurani, Joseph Palackal Mathew, Prasanth K, Visvesvaraya Appala Pentakota, Shagun Dusad
  • Patent number: 11908582
    Abstract: The description relates to a system for assessing the functional performance of an individual, the system comprising a sensor device; a monitoring system, connectable to the sensor device, configured to receive signals coming from the sensor device, pre-process the signals received from the sensor device, extract the main features of the pre-processed signals to be used as predictor variables, assess the functional performance of an individual based on the predictor variables.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: February 20, 2024
    Assignee: ADMINISTRACIÓN GENERAL DE LA COMUNIDAD AUTÓNOMA DE EUSKADI
    Inventors: Jaime Herran Planchuelo, Larraitz Añorga Gomez, Itziar Vergara Micheltorena, Kalliopi Vrotsou, Marcos Jesus Arauzo Bravo, Ander Matheu Fernández
  • Patent number: 11901898
    Abstract: A disclosed apparatus for accomplishing such a task may include (1) a circuit board incorporated into a module designed for insertion into slots of computing devices, (2) at least one conductive contact disposed on the circuit board, (3) a counter circuit disposed on the circuit board and communicatively coupled to the conductive contact, wherein the counter circuit comprises (A) a signal-change detector that detects signal changes as the module is inserted into one of the slots of the computing devices and (B) a counter device that maintains a dynamic count indicative of a number of times that the module has been inserted into one of the slots of the computing devices based at least in part on the signal changes, (4) a battery electrically coupled to the counter circuit, wherein the battery powers the counter device prior to the insertion. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: February 13, 2024
    Assignee: Juniper Networks, Inc.
    Inventors: John Kenney, Bo Mi, Ryan Holmes
  • Patent number: 11901905
    Abstract: The present disclosure provides for calibrating clock signals in an unmatched data input system. In various embodiments, an unmatched data input system uses multi-delay circuits to calibrate a clock signal distributed to various input/outputs in the unmatched data input system. These multi-delay circuits can include coarse delay circuits and fine delay circuits that provide a broad range as well as accurate delay capabilities. Through the use of these multi-delay circuits, the unmatched data input system can optimally align a clock signal with its associated data signal across multiple input/outputs.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: February 13, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Tianyu Tang
  • Patent number: 11881059
    Abstract: A system and method for detecting abnormal operating conditions in a machine through the analysis and comparison of radar areas after the transformation of waveform data collected from machine parts. An example embodiment is configured to: generate a monitoring signal in response to the behavior of a machine while the machine is in operation; simultaneously monitor two or more spectrums in the monitoring signal; collect data for two ore more spectrums at times when the machine is operating normally to establish an operational baseline of said machine; identify a respective energy level in each of the two or more spectrums; process waveform data corresponding to each of said identified energy levels into a Fast Fourier Transform radar plot; determine an area that corresponds to the FFT radar plot; correlate changes in the area of the FFT radar plot with changes in spectrum data and changes in the operation of the machine.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: January 23, 2024
    Assignee: ONLINE DEVELOPMENT, INC.
    Inventors: Keith A. Walton, Kai T. Bouse
  • Patent number: 11876499
    Abstract: A method of stabilizing a variable filter for an analog electromagnetic signal against circuit oscillation includes the steps of: providing a signal loop comprising a signal input, a signal output, and a plurality of variable circuit elements connected in the signal loop, the plurality of variable circuit elements comprising an adjustable resonator and an adjustable gain block, the signal loop having a variable frequency response that is characterized by a central frequency, a frequency passband, a response Q, and an operating point and a resonator response curve that are plottable in a Cartesian s-plane having an origin, a real axis, and an imaginary axis; and maintaining stability of the variable filter within an operating range by controlling the adjustable resonator and the adjustable gain block such that, in the Cartesian s-plane, the resonator response curve satisfies an orthogonality stability condition.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: January 16, 2024
    Assignee: Anlotek Limited
    Inventor: Jorgen Staal Nielsen
  • Patent number: 11870450
    Abstract: An apparatus comprises a first circuit and a second circuit. The first circuit may be configured to generate an output signal having a first frequency in response to a voltage level of a first input signal and a value of a second input signal. The second circuit may be configured to determine the value of the second input signal based on a reference frequency signal, the first frequency of the output signal, a reference voltage, and a value representing a target frequency for the output signal.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: January 9, 2024
    Assignee: Ambarella International LP
    Inventors: Yueh Chun Cheng, Xuan Wang
  • Patent number: 11863013
    Abstract: A method for selecting a power source for a load is provided. The method includes monitoring the primary power source, when the primary power source is providing power to the load, determining if a condition of the primary power source crosses a first threshold, when the condition crosses the first threshold, turning on a first power field effect transistor to couple a back-up power source to the load through a second power field effect transistor, when the primary power source is not providing power to the load, determining if a condition of the primary power source crosses a second threshold, and when the condition crosses the second threshold, switching off the first power field effect transistor to couple the primary power source to the load through a third power field effect transistor.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: January 2, 2024
    Assignee: CommScope Technologies LLC
    Inventor: Daryl A Coleman
  • Patent number: 11855619
    Abstract: An integrated circuit device includes: an integrated circuit module; a first field-effect transistor coupled between the integrated circuit module and a first reference voltage, and controlled by a first controlled signal; and a second field-effect transistor coupled between the integrated circuit module and the first reference voltage; wherein the second field-effect transistor is a complementary field-effect transistor of the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor are configured to generate a second reference voltage for the integrated circuit module according to the first control signal.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tzung-Yo Hung, Pin-Dai Sue, Chien-Chi Tien, Ting-Wei Chiang
  • Patent number: 11848679
    Abstract: The present application discloses a circuit for generating spread-spectrum synchronous clock signal. The circuit includes a frequency detector comprising a fraction controller configured to compare an input signal of a first frequency with a feedback signal of a second frequency in a loop of feedback to generate a first control signal and a second control signal alternately for determining a control word to track the first frequency and a phase-shift controller configured to register n levels for the first control signal and the second control signal to introduce n phase delays for changing a fraction part of the control word randomly to provide a broadened boundary. The circuit also includes a digitally controlled oscillator configured to generate a synthesized periodic signal based on a base time unit, the first frequency, and the control word, with the second frequency being locked within the broadened boundary of the first frequency.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: December 19, 2023
    Assignees: Beijing BOE Technology Development Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xiangye Wei, Liming Xiu
  • Patent number: 11843388
    Abstract: A Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal. Example embodiments include a CAN transmitter (100) comprising: an oscillator (101) configured to generate a clock signal having n equally spaced phases (clk_0, clk_120, clk_240), where n is an integer greater than 1; n Digital to Analog Converters, DACs (1021-3), each DAC having an input connected to one of the n phases of the clock signal and to a common data input line, each DAC being configured to provide an output signal that transitions between first and second output levels in M discrete steps upon being triggered by a transition of a signal on the data input line synchronized with the one of the n phases of the clock signal; and an output amplifier stage (103) configured to provide a differential CAN output signal from a combination of output signals from each of the n DACs (1021-3).
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: December 12, 2023
    Assignee: NXP B.V.
    Inventors: Johannes Petrus Antonius Frambach, Cornelis Klaas Waardenburg, Gerard Arie de Wit
  • Patent number: 11838023
    Abstract: A motor control system includes a variable voltage supply in signal communication with a direct current (DC) motor. The DC motor includes a rotor induced to rotate in response to a drive current generated by a variable supply voltage delivered by the voltage supply. The rotation of the rotor generates a mechanical force that drives a component. A ripple count circuit is configured to filter the drive current based on a rotational speed (?) of the rotor, and to generate a pulsed output signal indicative of the rotational speed (?) of the rotor and a rotational position (?) of the rotor.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: December 5, 2023
    Assignee: INTEVA FRANCE
    Inventors: François Breynaert, Simon Herpin, Mohamed Benderradji
  • Patent number: 11837769
    Abstract: An apparatus, including a waveguide, a first circuit, a second circuit. The waveguide is connected to the first circuit and the second circuit. The first circuit is located within a cryostat.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: December 5, 2023
    Assignee: Abu Dhabi University
    Inventors: Montasir Yousof Abdallah Qasymeh, Hichem El Euch
  • Patent number: 11831290
    Abstract: An inductive-capacitive filter includes a first insulating-conductive strip wound around a winding axis, where the first insulating-conductive strip includes a first conductive strip joined with a first insulating strip. An inductive-capacitive filter assembly includes a first and a second insulating-conductive strip concentrically wound around a winding axis, the first insulating-conductive strip including a first conductive strip joined with a first insulating strip, and the second insulating-conductive strip including a second conductive strip joined with a second insulating strip.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: November 28, 2023
    Assignee: WJLP COMPANY INC.
    Inventors: Weyman John Lundquist, Mary Elizabeth Clark