Patents Examined by Hai L. Nguyen
  • Patent number: 11067453
    Abstract: A circuit is disclosed that includes a capacitive element, a control circuit, and a first switch and a second switch. The capacitive element is configured to generate an output voltage at a terminal thereof. The control circuit is configured to generate a first control signal and a second control signal in response to a first temperature-dependent voltage, a second temperature-dependent voltage, and the output voltage. The first switch and the second switch are coupled to the capacitive element, and configured to be turned on or off in response to the first control signal and the second control signal respectively. The first switch and the second switch have different switching status from each other in a charge mode.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jaw-Juinn Horng, Szu-Lin Liu
  • Patent number: 11070352
    Abstract: A clock data recovery circuit includes a circuit that receives a data signal for which each of a plurality of potential levels is associated with a value of 2 bits or more, based on a result of a first comparison that compares the 3 or more first thresholds with the data signal at timing synchronized with a clock signal; a circuit that outputs a result of a second comparison that compares the data signal with a second threshold at the timing; a circuit that generates a phase difference signal indicating whether to advance or delay a phase of the clock signal, based on the result of the determination and the result of the second comparison; a filter that generates a phase adjusted value indicating an adjustment amount of the phase, based on the phase difference signal; and a circuit that adjusts the phase based on the phase adjusted value.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: July 20, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Nobuaki Kawasoe, Yoshiharu Yoshizawa, Manabu Yamazaki
  • Patent number: 11063600
    Abstract: A multi-stage clock generation circuit is disclosed. The circuit includes first and second ring oscillators. The ring oscillators include a corresponding plurality of delay elements coupled in series, with a plurality of shunt circuits in parallel with corresponding inverters. The shunt circuits include respective interpolation nodes, which are resistively coupled to input and output nodes of their corresponding inverters. The interpolation nodes of the first ring oscillator are coupled to delay element input and output nodes of the second ring oscillator. Similarly, the interpolation nodes of the second ring oscillator are coupled to delay element input and output nodes of the first ring oscillator.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: July 13, 2021
    Assignee: Apple Inc.
    Inventors: Wenbo Liu, Wei-Ming Lee, Sanjeev K. Maheshwari
  • Patent number: 11063471
    Abstract: A battery module is provided including a battery module connector configured to engage with a backplane connector on a backplane board associated with an uninterruptible power supply (UPS). When the battery module connector is engaged with the backplane connector a circuit is completed that instantaneously indicates to the UPS that the battery module is connected. When the battery module connector is disengaged from the backplane connector the circuit is opened and instantaneously indicates to the UPS that the battery module is disconnected.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: July 13, 2021
    Assignee: Eaton Intelligent Power Limited
    Inventors: Pradeep Kumar Nandam, David Glenn Miller
  • Patent number: 11061430
    Abstract: A spread spectrum clock generating system is provided. The digital frequency detecting unit is configured for receiving a reference signal and a feedback signal and for comparing the reference signal and the feedback signal to generate a frequency difference signal. The digital loop filtering unit is signally connected to the digital frequency detecting unit and outputs a clock controlling signal based on the frequency difference signal. The digital spread spectrum controlling unit is configured for receiving the reference signal to output a spread spectrum signal. The digital-analog converting unit is configured for converting the clock controlling signal to a first controlling signal and for converting the spread spectrum signal to a second controlling signal. The analog controlled oscillating unit is configured for receiving the first controlling signal and the second controlling signal to output a spread spectrum clock signal.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: July 13, 2021
    Assignee: SI EN TECHNOLOGY (XIAMEN) LIMITED
    Inventors: Tsen-Shau Yang, Chen-Ya Peng
  • Patent number: 11054446
    Abstract: The present disclosure provides a system and method including: a first USB port and one or more second USB ports provided on the multi-port adapter; an AC-DC conversion configured to measure a first load current at the first USB port; a plurality of buck-boost mode power conversion units, each configured to measure a second load current at a corresponding one or more second USB ports; and a system controller configured to measure the first load current and the one or more second load currents, wherein the system controller is configured to compare and adjust the measured first load current and the measured one or more second load currents to, respectively, a first rated current and a corresponding second rated current for each of the one or more second USB ports.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: July 6, 2021
    Assignee: SILICONCH SYSTEMS PVT LTD
    Inventors: Burle Naga Satyanarayana, Rakesh Kumar Polasa, Shubham Paliwal, Satish Anand Verkila
  • Patent number: 11055627
    Abstract: Methods, systems, and apparatus for implementing a unitary quantum gate on one or more qubits. In one aspect, a method includes the actions designing a control pulse for the unitary quantum gate, comprising: defining a universal quantum control cost function, wherein the control cost function comprises a qubit leakage penalty term representing i) coherent qubit leakage, and ii) incoherent qubit leakage across all frequency components during a time dependent Hamiltonian evolution that realizes the unitary quantum gate; adjusting parameters of the time dependent Hamiltonian evolution to vary a control cost according to the control cost function such that leakage errors are reduced; generating the control pulse using the adjusted parameters; and applying the control pulse to the one or more qubits to implement the unitary quantum gate.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: July 6, 2021
    Assignee: Google LLC
    Inventors: Yuezhen Niu, Hartmut Neven, Vadim Smelyanskiy, Sergio Boixo Castrillo
  • Patent number: 11057039
    Abstract: The present disclosure relates to a method for quadrature error correction using a frequency divider circuit. The method comprises delaying input of data to master input terminals and/or slave input terminals of the frequency divider circuit for correcting a quadrature error between the in-phase and quadrature-phase output signals.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Marcel A. Kossel, Vishal Khatri, Pier Andrea Francese, Matthias Braendli
  • Patent number: 11057000
    Abstract: A superconducting device that mixes surface acoustic waves and microwave signals and techniques for fabricating the same are provided. A superconducting device can comprise a superconducting surface acoustic wave resonator and a superconducting microwave resonator. The superconducting device can also comprise a Josephson ring modulator coupled to the superconducting surface acoustic wave resonator and the superconducting microwave resonator. The Josephson ring modulator can be a dispersive nonlinear three-wave mixing element.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: July 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Baleegh Abdo
  • Patent number: 11050343
    Abstract: A power supply includes: a power factor correction circuit that includes a capacitor and converts an input voltage, produced by rectifying an AC input voltage, to a DC, output voltage; a current detector that detects an inflow current for the power factor correction circuit and outputs a current detection signal; an output voltage detector that detects the output voltage and outputs an output voltage detection signal; a voltage difference detector that detects a voltage difference between maximum and minimum values of a pulsation component of the output voltage detected from the output voltage detection signal; a working life determiner that compares the voltage difference and a threshold and gives notification of end of life of the capacitor when the voltage difference reaches the threshold; and a threshold updater that updates the threshold in keeping with the detected inflow current detected based on the current detection signal.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: June 29, 2021
    Assignee: TDK CORPORATION
    Inventor: Eiji Takegami
  • Patent number: 11043937
    Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: June 22, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Badarish Mohan Subbannavar, Arnab Khawas, Suvam Nandi
  • Patent number: 11029716
    Abstract: In one embodiment, an apparatus includes: an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; a loop circuit coupled to the amplifier, where the loop circuit is to receive the comparison signal and provide a regulated voltage to the amplifier as the feedback voltage in a first mode of operation, and in a second mode of operation to provide a predetermined feedback ratio point to the amplifier as the feedback voltage; and an output device coupled to the amplifier. The output device may be configured to receive a supply voltage and the comparison signal and output the regulated voltage at an output node based at least in part on the comparison signal.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: June 8, 2021
    Assignee: Silicon Laboratories Inc.
    Inventors: Hua Beng Chan, Rex Tak Ying Wong, Ricky Setiawan
  • Patent number: 11025300
    Abstract: Aspects of the subject disclosure may include, for example, a transmission medium having a core. A conductive layer forms an uninsulated outer surface of the transmission medium. The conductive layer is configured to impede accumulation of water to support propagation of first electromagnetic waves guided by the uninsulated outer surface. Other embodiments are disclosed.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: June 1, 2021
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Farhad Barzegar, Donald J. Barnickel, Robert Bennett, Irwin Gerszberg, Paul Shala Henry, Thomas M. Willis, III
  • Patent number: 11018510
    Abstract: Systems and methods that can be retrofitted into an existing wired electrical system replacing existing switches whether as a standalone single switch or part of a multi-way switch configuration that can be controlled locally nominally by touch, controlled remotely by a remote, or controlled remotely by a computer. The systems and method provide that the switches establish a local network allowing for retrofit or construction of a structure or facility with electrical system automation without the need for additional wiring.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: May 25, 2021
    Assignee: Ivani, LLC
    Inventors: Matthew Wootton, Christopher Nissman, John Wootton, Justin McKinney
  • Patent number: 11018676
    Abstract: Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Fangxing Wei, Khushal Chandan, Dan Shi, Michael Allen
  • Patent number: 11018647
    Abstract: An electrical filter structure for forwarding an electrical signal from a first port to a second port in a frequency selective manner, wherein the filter is an edge-coupled filter, the filter comprising: a plurality of coupled line sections coupled in a series, comprising at least a first coupled line section and a last coupled line section; wherein the first port is connected with the first of the coupled line sections using a first transmission line; wherein the second port is connected with the last of the coupled line sections using a second transmission line; wherein the electrical filter comprises an open stub; wherein a length of the open stub is chosen such that an electrical length of the open stub is equal, within a tolerance of +/?20 percent, to a fourth of a wavelength of a signal having a frequency of twice a passband center frequency of the filter.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: May 25, 2021
    Assignee: Advantest Corporation
    Inventor: Giovanni Bianchi
  • Patent number: 11011244
    Abstract: The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire. One of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain thereof is connected to the gate electrode of the second transistor, and a gate electrode thereof is connected to a fourth wire.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: May 18, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 11012078
    Abstract: An IQ signal source (100) includes: a Q-VCO (3) having a first VCO (1) and a second VCO (2), the IQ signal source (100) outputting an I signal and a Q signal by electrically coupling the first VCO (1) and the second VCO (2) with each other; a first PLL (10) for comparing a frequency of the I signal or the Q signal with a frequency of a reference signal input from the outside of the IQ signal source (100) and outputting a voltage depending on a result of the comparison; and a second PLL (9) for detecting an IQ phase difference and outputting a voltage depending on the IQ phase difference. The IQ phase difference converges to 90 degrees in dependence on the output voltage of the first PLL (10) and the output voltage of the second PLL (9).
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: May 18, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akihito Hirai, Mitsuhiro Shimozawa
  • Patent number: 11007888
    Abstract: A vehicle include: an AC inlet configured to be connectable to an AC connector; a DC inlet configured to be connectable to a DC connector; a first actuator configured to perform a locking operation and an unlocking operation for an AC lid configured to cover the AC inlet; a second actuator configured to perform a locking operation and an unlocking operation for a DC lid configured to cover the DC inlet; a first electric power line; a second electric power line; a lock relay connected to one end of the first electric power line; and an unlock relay connected to one end of the second electric power line. The first actuator and the second actuator are connected in parallel with each other between the other end of the first electric power line and the other end of the second electric power line.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: May 18, 2021
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Noriaki Aburai
  • Patent number: 11005385
    Abstract: The disclosure provides an alternator and a rectifier thereof. The rectifier includes a transistor and a gate driving circuit. A control end of the transistor receives a gate voltage. The gate driving circuit generates the gate voltage according to a voltage difference between an input voltage and a rectified voltage. The gate driving circuit detects an initial time point when the voltage difference is smaller than a first preset threshold voltage, provides the gate voltage to turn on the transistor during a first time period after the initial time point, and sets the voltage difference to be equal to a first reference voltage. The gate driving circuit sets the voltage difference to be equal to a second reference voltage through adjusting the gate voltage during a second time period after the first time period.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: May 11, 2021
    Assignee: ACTRON TECHNOLOGY CORPORATION
    Inventors: Wei-Jing Chen, Shang-Shu Chung, Yen-Yi Chen, Huei-Chi Wang