Abstract: A motor control system includes a variable voltage supply in signal communication with a direct current (DC) motor. The DC motor includes a rotor induced to rotate in response to a drive current generated by a variable supply voltage delivered by the voltage supply. The rotation of the rotor generates a mechanical force that drives a component. A ripple count circuit is configured to filter the drive current based on a rotational speed (?) of the rotor, and to generate a pulsed output signal indicative of the rotational speed (?) of the rotor and a rotational position (?) of the rotor.

Abstract: An apparatus, including a waveguide, a first circuit, a second circuit. The waveguide is connected to the first circuit and the second circuit. The first circuit is located within a cryostat.

Abstract: An inductive-capacitive filter includes a first insulating-conductive strip wound around a winding axis, where the first insulating-conductive strip includes a first conductive strip joined with a first insulating strip. An inductive-capacitive filter assembly includes a first and a second insulating-conductive strip concentrically wound around a winding axis, the first insulating-conductive strip including a first conductive strip joined with a first insulating strip, and the second insulating-conductive strip including a second conductive strip joined with a second insulating strip.

Abstract: A mechanical energy-based self-powering counting system is provided. The system includes an electromagnetic power generator, a count measuring circuit, a count energy supply circuit, a controller and a wireless transmission module. The electromagnetic power generator is driven by an external device and produces an electric signal and outputs the electric signal to the controller after passing it through the count measuring circuit. The controller processes the received signal, updates a count according to certain programming rules and sends data to the wireless transmission module. The energy from the electromagnetic power generator flowing through the count measuring circuit can supply power to the controller. An energy storage module in the count energy supply circuit performs voltage feedback on the controller. The controller monitors the voltage of the energy storage module to control whether it enters a charging state.

Abstract: A system for filter enhancement, preferably including one or more analog taps and a controller, and optionally including one or more couplers. The system is preferably configured to integrate with a filter, such as a passband filter or other frequency-based filter. The system can be configured to integrate with an RF communication system, an RF front end, or any other suitable RF circuitry. A method for filter enhancement, preferably including configuring one or more analog taps, and optionally including calibrating a system for filter enhancement and/or receiving temperature information.

Abstract: A bidirectional power conversion system includes three power conversion ports. A first power conversion port includes a power factor correction device and a primary power conversion network. A second power conversion port includes a plurality of switches and a plurality of diodes, wherein an output voltage of the second power conversion port is regulated through adjusting an output voltage of the power factor correction device as well as through adjusting an operating parameter of the primary power conversion network. A third power conversion port includes a first switch network and a power regulator connected in cascade, wherein the first power conversion port, the second power conversion port and the third power conversion port are magnetically coupled to each other through a transformer.

Abstract: Bias adjusting circuits (1_(2k-1), 1_2k) (where k is an integer equal to or greater than 1 and equal to or less than N, and N is an integer equal to or more than 2) adjust DC bias voltage of at least one of clock signals such that a duty ratio, which is a ratio between a period in which a clock signal is High as to a clock signal and a period in which the clock signal is Low thereasto, becomes (2N?2k+1):(2k?1). Sampling circuits switch between a track mode in which an output signal tracks an input signal, and a hold mode in which a value of the input signal at a timing of switching from the track mode to the hold mode is held and output, in accordance with clock signals output from the bias adjusting circuits (2_1 to 2_2N).

Abstract: A clock generator can include a Fin Field Effect Transistor (FinFET) oscillator and a phased-locked loop (PLL). The FinFET oscillator can generate a FinFET signal. The PLL can generate an output clock signal based on a reference clock signal and the FinFET signal.

Abstract: Described herein are systems and methods that allow for correcting a residual frequency offset in the GHz frequency range by using low-complexity analog circuit implementations of a broad-band frequency detector that comprises two analog polyphase filters in a dual configuration. Each filter comprises an RC network of cross-coupled capacitors that facilitate filters with opposite passbands and opposite stop-bands. In various embodiments, the outputs of the two filters are combined to obtain power metrics that when subtracted from each other, deliver a measure of the imbalance between the positive and negative halves of a frequency spectrum. Since the measure is substantially proportional to a frequency offset within a linear range spanning 5 GHz or more, the polyphase filters may be used in a broad-band frequency detector that, based on the measure, adjusts the frequency offset.

Abstract: The present disclosure is directed to a digital phase-locked loop frequency synthesizer including: a digitally controlled voltage-controlled oscillator (DCO); a reference oscillator; a digital phase detector; a DCO control module comprising a plurality of registers each arranged to control the frequency of the signal with a predetermined resolution; a first feedback loop arranged to provide a first feedback path between the output of the DCO and the digital phase detector; and a second feedback loop arranged to provide a second feedback path between the first register output and the second register input, the second feedback loop comprising an adder module arranged to change a value of the second register based on the first register output to maximize a DCO frequency output range provided by the first register.

Abstract: A reversible superconducting circuit includes two Josephson transmission lines. Inductors connect Josephson Junctions in the array. Each transmission line passes a fluxon along the Junctions. The circuit includes an interface with first and second shunt capacitors coupled to the first and second transmission lines, and a third shunt capacitor, forming a connecting circuit with the first and second shunt capacitors. The shunt capacitors include Josephson junctions in parallel. The connecting circuit receives an input fluxon and transmits an output fluxon. The circuit also includes a Josephson Junction and inductor in parallel with the third shunt capacitor, forming a storage circuit. The storage circuit stores a SFQ. The output fluxon has polarity based on the SFQ stored when the first fluxon is received. The input fluxon causes the polarity of the stored SFQ to be the same as the polarity of the input fluxon, immediately after the input fluxon is received.

Abstract: A capacitive detection device includes a capacitive sensor having a sense electrode and an auxiliary electrode that are arrangeable in the vicinity of an electric heater member for mutual capacitive coupling. The capacitive detection device has a signal voltage source providing an alternating measurement voltage, a complex impedance measurement circuit for measuring complex sense currents and for determining a complex impedance based on the measured complex sense current, and for electrically connecting the auxiliary electrode either with the reference voltage or with the guard signal.

Abstract: In described examples, a phase locked loop (PLL) has a first phase detector cell (PD) that has a gain polarity. The first PD cell has a phase error output and inputs coupled to a reference frequency signal and a feedback signal. A second PD cell has an opposite gain polarity. The second PD cell has a phase error output and inputs coupled to the reference frequency signal and the feedback signal. A loop filter has a feedforward path and a (lossy) integrating path coupled to an output of the filter. The feedforward path has a third PD cell that has phase error output AC-coupled to the filter output. The integrating path includes an opamp that has an inverting input coupled to the first PD cell phase error output and a non-inverting input coupled to the second PD cell phase error output.

Abstract: A tunable slope equalizer comprising a waveguide (e.g., rectangular waveguide) and posts (e.g., cylindrical posts) configured to move inside the internal cavity of the waveguide is presented. The degree of depth the posts may be inserted into the cavity of the waveguide may determine the orientation of the frequency response slope, e.g., positive or negative, and the maximum (or approximately maximum) insertion loss at minimum (or approximately minimum) or maximum (or approximately maximum) operating frequency, respectively. Being a mechanical device, the tunable slope equalizer may be fabricated at a relatively higher level of precision, leading to lower variances in performance over production.

Abstract: A device for synchronizing a periodic high frequency power signal (18) and an external reference signal (10). The device comprises a phase control circuit (100) and a digital oscillator circuit (130). The digital oscillator circuit (130) is connected to the phase control circuit (100). The digital oscillator circuit (130) comprises means for generating the periodic high frequency power signal (18) dependent on the control signal from the phase control circuit. The phase control circuit (100) is configured to determine a phase difference of the periodic high frequency power signal (18) and the external reference signal (10).

Abstract: A dual start control circuit for auxiliary inverters of a railway vehicle is provided. An external dual circuit is designed for controlling a start and stop of the auxiliary inverters; and an APS START signal is added to start conditions of the auxiliary inverters. When a start-stop switch is turned to an “on” position, an APS start train line is electrified, APS start relays in cabs at both ends are electrified and corresponding normally-open contacts of the APS start relays are closed, a self-locking circuit is kept electrified, the APS start train line is kept electrified, and a start signal is transmitted to the auxiliary inverters through a hard wire; and when the start-stop switch is turned to an “off” position, an APS stop train line is electrified, APS stop relays in the cabs at both ends are electrified and corresponding normally-closed contacts of the APS stop relays are disconnected.

Abstract: A crystal device includes a bearing base, an integrated chip and a conductive adhesive unit. The bearing base includes a conductive seat. The integrated chip includes a principal reference plane facing the conductive seat, and having a first major axis. The conductive adhesive unit has a second major axis and an aspect ratio, and is at least partly disposed between the conductive seat and the integrated chip. The aspect ratio ranges from 1.1 to 1.9. The principal reference plane further has a perpendicular projection straight line defined according to the second major axis. A practical angle is included by the first perpendicular projection straight line and the first major axis, and ranges from 0 degree to 90 degrees.

Abstract: In an imaging system, a differential signal transmission circuit is configured to output a first signal to a first signal line in an image output period and is configured to output a second signal to a second signal line in the image output period. The first signal and the second signal are included in a differential signal. A signal output circuit is configured to output a second clock signal to the first signal line in a blanking period different from the image output period and is configured to output a second control signal to the second signal line in the blanking period. In a PLL, connection between a charge pump and a loop filter is controlled on the basis of the second control signal output to the second signal line.

Abstract: Methods and systems for generating a product packaging model for a product offering of a set of product items associated with a merchant account. At an e-commerce platform, a trigger event is detected and, in response, two or more product items are automatically selected to form a kit that makes up the product offering. Model data for the two or more product items and packaging parameters are used to automatically select a packaging option and to build a product packaging model that is sent to the merchant account. The product packaging model may be a three-dimensional computer model of the kit containing the two or more product items.

Abstract: A flip flop circuit includes a first master portion, a second master portion, at least one determining portion and a slave portion. The first master portion is configured to operate at a first mode and to receive a first input and generate first master outputs. The second master portion is configured to operate at a second mode and to receive a second input and generate second master outputs. The at least one determining portion is configured to receive at least one enable signal, and has determining inputs and determining outputs. The determining inputs are connected to the first master outputs and the second master outputs. The determining portion is configured to determine the determining outputs being the first master outputs or the second master outputs according to the at least one enable signal. The slave portion is configured to receive the determining outputs and generate an output signal.