Abstract: Methods, systems, circuits, devices, and apparatuses are described for auto-detection and adaptive configuration of high-definition multimedia interface (HDMI) ports. Unique systems and circuits allow HDMI repeaters to automatically detect if an HDMI device that has been connected thereto, via an HDMI port, is an HDMI source (source mode) or an HDMI sink (sink mode). The unique systems and circuits may be adaptively configured to allow the HDMI port to function as an HDMI input or an HDMI output based on the automatic detection. Methods corresponding to the functions performed by the systems and apparatuses are provided, and computer readable storage media with computer program instructions encoded thereon for enabling processing devices to perform the methods are also provided.

Abstract: A memory system includes a memory controller comprising n (where n>2) first data input/output terminals, a first semiconductor chip comprising n second data input/output terminals, each of the second data input/output terminals being connected to a respective one of the first data input/output terminals, and a second semiconductor chip comprising n third data input/output terminals, each of the third data input/output terminals being connected to a respective one of the first data input/output terminals. When a first request signal is output from the memory controller, status data of the first semiconductor chip is output from a first of the second data input/output terminals that is connected to a first of the first data input/output terminals, and status data of the second semiconductor chip is output from a second of the third data input/output terminals that is connected to a second of the first data input/output terminals.

Abstract: An SR-IOV-supported storage resource access method is disclosed, the method includes: consolidating a storage medium as a unified storage resource, and dividing the unified storage resource into multiple storage sub-resources; allocating the storage sub-resources to at least one of a PF or a VF according to a preset allocation rule, and maintaining a resource allocation table including a mapping relationship between the storage sub-resources and at least one of PF or VF; receiving a host command sent by a virtual machine to a destination VF or by a virtual machine monitor to a destination PF; and searching the resource allocation table according to destination VF or destination PF, and performing, on a storage sub-resource corresponding to destination PF or destination VF and according to the mapping relationship between the storage sub-resources and the PF or the VF in the resource allocation table, an operation corresponding to the host command.

Abstract: An apparatus includes a first interface configured to receive a first message from a host device or from a data storage device. The apparatus further includes a buffer and a second interface. The buffer is coupled to the first interface and is configured to store the first message. The second interface is coupled to the buffer and is configured to provide the first message to the data storage device or to the host device, respectively. The second interface is further configured to provide, at a time based on a performance metric associated with the first message, a second message to the data storage device or to the host device, respectively. The apparatus further includes a circuit configured to determine the performance metric.

Abstract: A microcontroller (2) has a processor (6), peripherals (18, 20, 22, 24, 26), a programmable peripheral interconnect (PPI) (10), an event-generating unit (EGU) (17), and a memory (8). The peripherals respond to task signals from the PPI. The EGU responds to a predetermined change to the contents of an event-generating register (57, 59) by signalling an event to the PPI. Stored PPI mappings can map an EGU event to a task of one of the peripherals. Mappings from one EGU event to two or more peripheral tasks cause the PPI to respond to an event signal from the EGU by sending the respective task signals within a maximum time limit. Software in the memory comprises instructions to store such mappings in a mapping memory, and to make the predetermined change to the contents of the event-generating register. In another aspect, an interrupt-generating unit (17) is arranged to send an interrupt to the processor (6) in response to receiving a task signal from the PPI (10).

Abstract: In general, embodiments of the technology relate to a method and system for performing fast ordered writes in a storage appliance that includes multiple separate storage modules. More specifically, embodiments of the technology enable multicasting of data to multiple storage modules in a storage appliance, where the order in which the write requests are processed is the same across all storage modules in the storage appliance.

Abstract: Embodiments of the inventive concept include Open Cloud Server (OCS)-compliant and other enterprise servers having high-density modular non-volatile flash memory blades and associated multi-card modules. A modular non-volatile flash memory blade can be seated within a 1 U tray. The flash memory blade can include a server motherboard and multiple non-volatile flash memory blade multi-card modules. Each of the multi-card modules can include a printed circuit board, a switch coupled to the printed circuit board, a module power port, an input/output port, and riser card slots to receive solid state drive riser cards. The solid state drive riser cards can be seated within a corresponding riser card slot of the multi-card modules, and can each include multiple solid state drive chips. The server motherboard can communicate with the solid state drive chips via the cable connector riser cards and associated cables.

Abstract: Systems and methods are provided that may be implemented in-situ and on-chip to capture a digital signal eye of a serial transmit signal produced by a transmitter circuit of integrated SerDes PHY transceiver circuitry. In one example, a serial transmit signal produced by a transmitter side circuit of an integrated SerDes PHY transceiver circuit may be looped back on chip to the receiver side circuit of the same SerDes PHY transceiver circuit such that an integrated digital eye monitor circuit of the SerDes receiver circuit may capture the digital eye of the serial transmit signal of the same SerDes PHY circuit. In another example, a digital eye monitor circuit may be integrated on the transmitter side of an integrated SerDes PHY transceiver circuit such that a serial transmit signal produced by the transmitter side circuit of may be captured on-chip.

Abstract: A memory network includes a plurality of memory nodes each identifiable by an ordinal number m, and a set of links divided into N subsets of links, where each subset of links is identifiable by an ordinal number n. For each subset of the plurality of N subsets of links, each link in the subset connects two memory nodes that have ordinal numbers m differing by b(n-1), where b is a positive number. Each of the memory nodes is communicatively coupled to a processor via at least two non-overlapping pathways through the plurality of links.

Abstract: A packet data processing method, apparatus, and system. The method is executed by a first processing apparatus, and includes: acquiring packet data that needs to be processed, where the packet data that needs to be processed includes first packet data information and second packet data, and the first packet data information includes a header of the packet data that needs to be processed and a storage address of the packet data that needs to be processed in the first processing apparatus; sending the first packet data information to a second processing apparatus; and receiving first packet data information (includes an updated header after being processed and the storage address) processed by the second processing apparatus, and generating finished packet data using the first packet data information processed by the second processing apparatus and the second packet data.

Abstract: A data processing system includes a plurality of data processing devices that perform in parallel data processing on the basis of initial setup data. The data processing devices each has a unique ID and includes a plurality of registers that store the initial setup data and a transfer circuit. The transfer circuit receives packets including a payload that is the initial setup data, shared information, a destination ID and a destination address and, when the shared information indicates that the payload is the initial setup data to be set commonly into the plurality of the data processing devices including its own data processing device, transfers the payload to the register that the destination address indicates irrespective of mismatching between the destination ID and its own ID.

Abstract: Systems and methods are disclosed to delete a command queue, in accordance with certain embodiments of the present disclosure. An apparatus may comprise a circuit configured to receive a queue deletion indicator from a host device, including a queue identifier for a selected command queue to be deleted. The circuit may abort each command associated with the selected command queue and pending at the apparatus based on the queue identifier. Commands associated with the selected queue may be identified in a command table and flagged with an abort bit, which may signal an I/O processing pipeline to abort the command when encountered. The circuit may verify that no commands associated with the selected command queue remain pending at the apparatus, and send a completion indicator to notify the host device that the selected command queue is deleted.

Abstract: Provided is an electronic control unit including: a master microcomputer having a master memory (23) that includes a master target data area (A7), a plurality of transmission master banks (A2, A3), a transmission master information area (A1), a reception slave information area (A4) and a plurality of reception slave banks (A5, A6); and a slave microcomputer having a slave memory (33) that includes a slave target data area (B7), a plurality of transmission slave banks (B5, B6), a transmission slave information area (B4), a reception master information area (B1) and a plurality of reception master banks (B2, B3).

Abstract: An apparatus having an interface and a circuit is disclosed. The interface may be connectable to a plurality of counters and a plurality of pipelines. The circuit may be configured to increment the counters associated with a first data unit in response to the first data unit being available in a buffer, and monitor a plurality of decrements of the counters by the pipelines. Each pipeline may decrement a respective counter when finished with the first data unit in the buffer. The circuit may also be configured to block the pipelines from processing a second data unit in the buffer until all of the counters associated with the first data unit have been decremented.

Abstract: A method to share remote DMA (RDMA) pointers to a key-value store among a plurality of clients. The method allocates a shared memory and accesses the key-value store with a key from a client and receives an information from the key-value store. The method further generates a RDMA pointer from the information, maps the key to a location in the shared memory, and generates a RDMA pointer record at the location. The method further stores the RDMA pointer and the key in the RDMA pointer record and shares the RDMA pointer record among the plurality of clients.