Patents Examined by Harry Z Wang
  • Patent number: 10789144
    Abstract: According to one embodiment, a supervisory circuit includes a trigger determination circuit and a trigger table. The trigger determination circuit receives signal processing signals outputted from a plurality of signal processing circuits as trigger signals, determines whether processing operations by the signal processing circuits are executed in a predetermined order, and outputs an interrupt signal when detecting a trigger signal out of setting. The trigger table is provided with trigger-specific tables corresponding to the respective signal processing circuits, reads a trigger setting to occur next based on a trigger determined as being correct by the trigger determination circuit, and outputs a table read signal to the trigger determination circuit.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 29, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akihiro Kobayashi, Makoto Kanda, Shigeru Itoh, Hiroshi Nishikawa, Wataru Furuichi, Kiyoshige Taga, Itsuro Nomura
  • Patent number: 10776294
    Abstract: In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: September 15, 2020
    Assignee: Atmel Corporation
    Inventors: Guillaume Pean, Vincent Debout, Marc Maunier
  • Patent number: 10769086
    Abstract: A recording medium to be used by being connected to a digital device includes a local bus, a plurality of recording units, an information storage unit, and a communication unit. The local bus has a plurality of switches or bridges. The plurality of recording units are connected to the local bus. The information storage unit stores information indicating a bus configuration of the local bus. The communication unit is used for transferring the information to and from the digital device. After the recording medium is inserted into the digital device, the bus configuration of the local bus is reconstructed based on the information acquired from the communication unit via the information storage unit by the digital device.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: September 8, 2020
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hideaki Yamashita, Takeshi Otsuka, Masanori Mitsuzumi
  • Patent number: 10761770
    Abstract: A data management method includes allocating a buffer for an application based on request information associated with data requested by the application, storing sensor data corresponding to the request information in the buffer, and transferring the sensor data stored in the buffer to the application.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jongwook Lee
  • Patent number: 10747445
    Abstract: A memory system includes a non-volatile memory, a data buffer in which data read out from the nonvolatile memory are stored prior to transmission to an initiator that is requesting the data, a port through which the initiator sends a request for the data and through which the data in the data buffer are transmitted to the initiator. When the port is connected to a first initiator at a time both first data requested by the first initiator and second data requested by a second initiator are stored in the data buffer and the second data become ready for transmission prior to the first data, the second data are transmitted through the port prior to the first data.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: August 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Kikuchi, Kazuhito Okita
  • Patent number: 10740002
    Abstract: An apparatus for recording data received in serial form is provided. The apparatus includes a data logging port, an external access port, a first memory, and a command memory and a state machine executing on a processor internal to the apparatus, that writes the data, received in serial form through the data logging port, to the first memory while locking out access to the first memory via the bus interface and the command memory. The bus interface and the command memory are configured to read the first memory, when not locked out, in accordance with a command placed in the command memory through the bus interface. A method performed by the apparatus is also provided.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: August 11, 2020
    Assignee: Arista Networks, Inc.
    Inventors: Charles Melvin Aden, Robert J. Marinelli
  • Patent number: 10721302
    Abstract: A computer network-storage protocol system, including at least one initiator device having an initiator block layer and an initiator network layer interfacing with a first network driver; at least one target device having a target block layer and a target network layer interfacing with a second network driver; a plurality of network interface controllers (NICs) interfacing with the first network driver and the second network driver; a plurality of distinct channels, each channel establishing a connection between the initiator device and the target device and being configured to transmit packets between the initiator device and the target device, wherein each channel is mapped to only one NIC; and wherein the initiator block layer includes at least one request message buffer and at least one data message buffer.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: July 21, 2020
    Assignee: FOUNDATION FOR RESEARCH AND TECHNOLOGY—HELLAS (FORTH)
    Inventors: Angelos Bilas, Maria Pilar Gonzalez Ferez
  • Patent number: 10708265
    Abstract: Methods, systems, and computer-readable media for batch registration and configuration of devices are disclosed. A plurality of devices are detected over one or more networks. Data indicative of the plurality of devices is provided through a user interface. Through the user interface, user input is received that indicates a selected plurality of the devices. The selected plurality of the devices are registered with a service provider environment. The selected plurality of the devices are authenticated using device-specific credentials and registered for device-specific accounts with the service provider environment. A configuration profile is deployed to the selected plurality of the devices.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: July 7, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Surabhi Raje, Krishnamurthy Ganesan, Yu-Hsiang Cheng, Ruoyu Fei, Jingyu Ji, Milo Oostergo, Aapo Juhani Laitinen, Collin Charles Davis, Karthik Bellur
  • Patent number: 10691628
    Abstract: Various examples of the present technology provide systems and methods for incorporating a switch card and adapter cards in a server system to provide flexible HDD and SSD supports. More specifically, a server system comprises a switch card having at least two different types of interfaces (e.g., a Serial Attached SCSI (SAS) interface, a serial ATA (SATA) interface, or a Peripheral Component Interconnect Express (PCIe) interface), and a controller that comprises a first Central Processing Unit (CPU) and a second CPU. The first CPU is connected to a first adapter card while the second CPU is connected to a second adapter card. The first adapter and the second adapter are coupled to the switch card of the server system.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: June 23, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Fa-Da Lin, Chih-Wei Yu
  • Patent number: 10684776
    Abstract: A method determines a configuration for inter-processor communication for a heterogeneous multi-processor system. The method determines at least one subgraph of a graph representing communication between processors of the heterogeneous multi-processor system. For each subgraph the method (i) determines a plurality of subgraph design points. Each subgraph design point has a variation of channel mapping between any two of the processors in the subgraph by selecting from first-in-first-out (FIFO) memory and shared cache, and varying the shared cache and a local memory associated with at least one of the processors according to the channel mapping; and (ii) selects a memory solution for the subgraph, based on a cost associated with the selected memory solution. The method then determines a configuration for the graph of the heterogeneous multi-processor system, based on the selected memory solutions, to determine the configuration for inter-processor communication for the heterogeneous multi-processor system.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: June 16, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kapil Batra, Yusuke Yachide, Haris Javaid, Sridevan Parameswaran, Su Myat Min Shwe
  • Patent number: 10671549
    Abstract: A device includes a connector including first and second portions, each being configured to establish an independent data connection with a portion of first and second connectors in an external device, and a controller. When the first portion is connected with a third portion of the first external connector, and a request to connect with the second portion is received from the second external connector, the controller determines whether or not to accept the request, and transmit an acceptance signal or a rejection signal to the second external connector through the second portion, according to the determination result.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: June 2, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi Kikuchi
  • Patent number: 10666866
    Abstract: An apparatus includes an interface and a circuit. The interface may be connectable to (i) a plurality of counters and (ii) multiple pipelines. The circuit may be configured to (i) increment two or more given counters of the counters associated with a plurality of first data units in response to the first data units being available in a buffer, where two or more of the pipelines each (a) reads a plurality of current units from the first data units and (b) decrements a respective one of the given counters in response to each read of one of the current units, (ii) monitor the decrements of the given counters and (iii) block a second data unit from being copied into the buffer until all of the given counters indicate that the buffer has room to hold the second data unit.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: May 26, 2020
    Assignee: Ambarella International LP
    Inventor: Kumarasamy Palanisamy
  • Patent number: 10654237
    Abstract: The invention relates to a system and to a method for identifying a compression roller column in a tableting machine having a machine processor. The system includes a plug-in connection which includes a receiving socket and a plug. The plug has at least one embedded controller, and data can be exchanged between the machine processor of the tableting machine and the embedded controller of the plug via the one plug-in connection. The plug and the receiving socket are arranged on the tableting machine. The plug can be connected to the receiving socket.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 19, 2020
    Assignee: Korsch AG
    Inventor: Walter Hegel
  • Patent number: 10635617
    Abstract: The subject technology provides for managing a data storage system. Commands are identified into as a first command type or a second command type. The commands identified as the first command type are assigned to a first queue, and the commands identified as the second command type are assigned to a second queue. After the commands from the first queue and the commands from the second queue are processed based on a scheduling ratio over a predetermined period of time, a write amplification factor, number of host read commands, and number of host write commands during the predetermined period of time are determined. The scheduling ratio is updated based on the write amplification, the number of host read commands, the number of host write commands, and a predetermined scheduling ratio factor. Subsequent commands are processed from the first queue and the second queue based on the updated scheduling ratio.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: April 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Scott Jinn, Yun-Tzuo Lai, Haining Liu, Yuriy Pavlenko
  • Patent number: 10614013
    Abstract: An input/output module is provided for a bus system having a socket, the five contact cups of which each may comprise an electrical contact, and a measuring device for detecting a connector of a four-wire data cable. The measuring device can be configured to detect, when a connector is inserted into the socket, whether the connector comprises four or five electrical contact pins which are each plugged into one of the contact cups and are electrically connected to the respective electrical contact of the contact cups. The measuring device may be configured to close a first and a second switching device only when five electrical contact pins are detected in order to apply a respective supply voltage from two DC voltage supplies to the corresponding plugged contact pins of the connector plugged into the socket via the respective electrical contacts of the contact cups.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: April 7, 2020
    Assignee: Beckhoff Automation GmbH
    Inventors: Holger Büttner, Thomas Rettig, Dirk Bechtel, Michael Jost, Christopher Pohl, Hans Beckhoff
  • Patent number: 10614016
    Abstract: Embodiments of a method, a device and a computer-readable storage medium are disclosed. In an embodiment, a method for operating a Controller Area Network (CAN) device involves in response to receiving bits of an arbitration field of a CAN data frame at the CAN device, selecting a timing engine from a plurality of timing engines and sampling subsequent bits of the CAN data frame using the selected timing engine. The timing engines have different sample clock frequencies.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: April 7, 2020
    Assignee: NXP B.V.
    Inventors: Rolf van de Burgt, Bernd Uwe Gerhard Elend
  • Patent number: 10614019
    Abstract: In general, embodiments of the technology relate to a method and system for performing fast ordered writes in a storage appliance that includes multiple separate storage modules. More specifically, embodiments of the technology enable multicasting of data to multiple storage modules in a storage appliance, where the order in which the write requests are processed is the same across all storage modules in the storage appliance.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 7, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Michael Nishimoto, Samir Rajadnya
  • Patent number: 10606778
    Abstract: A bus system is provided. The bus system includes a master device, a bus and a plurality of slave devices. The slave devices and the master device are electrically connected through the bus. The master device communicates with the slave devices by using a one-to-one communication mechanism. The slave devices communicate with the master device by using an arbitration mechanism in which one of the slave devices is selected to communicate with the master device.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: March 31, 2020
    Assignee: Nuvoton Technology Corporation
    Inventors: Chun-Wei Chiu, Chia-Ching Lu, Shih-Feng Huang, Ming-Che Hung
  • Patent number: 10592438
    Abstract: Technologies are disclosed herein that allow configuration of firmware by a firmware configuration device connected to a target computer. The firmware configuration device may emulate keystroke and/or mouse movement data to transmit firmware configuration data to the target computer. The target computer can also transmit status information and/or commands through keyboard status light signals.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: March 17, 2020
    Assignee: AMERICAN MEGATRENDS INTERNATIONAL, LLC
    Inventors: Kai Yau, Muthu Kumar Sathiyanesan
  • Patent number: 10572180
    Abstract: Systems and methods are disclosed to perform a function level reset in a memory controller, in accordance with certain embodiments of the present disclosure. In some embodiments, an apparatus may comprise a storage controller circuit configured to receive a function reset indicator from a host device, the function reset indicator identifying a selected storage controller function executing at a storage controller of the apparatus. The circuit may abort each command associated with the selected function and pending at the apparatus based on the function reset indicator, verify that no commands associated with the selected function remain pending at the apparatus, and clear registers associated with the selected function based on the determination that no commands associated with the selected function remain.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: February 25, 2020
    Assignee: Seagate Technology LLC
    Inventors: Shashank Nemawarkar, Balakrishnan Sundararaman, Chris Randall Stone, Charles Edward Peet, Allen Vestal, Siddharth Krishna Kumar