Abstract: An equalization time configuration method, applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used, includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

Abstract: Embodiments of the present disclosure relate to a system and a method for operating the system. The operating mode of a data processing circuit is changed according to a request indicating whether or not a first clock or a second clock is to be changed. Data transmitted from a first module to a second module inside the system is processed according to the operating mode of the data processing system. Accordingly, when the clock of one of modules included in the system changes, the module can quickly switch to a state in which the same can transmit/receive data to/from another module included in the system, and the performance of data transmission/reception between the modules included in the system can be optimized.

Abstract: In one embodiment, an apparatus includes: a peer-to-peer (P2P) control circuit to issue a P2P communication request to a bus master of a multi-drop interconnect to request authorization to send a P2P transaction to at least one slave device coupled to the multi-drop interconnect; a transmitter to transmit the P2P transaction to the at least one slave device when the bus master grants the authorization for the P2P transaction; and another transmitter to output the clock signal to the multi-drop interconnect during the P2P transaction. Other embodiments are described and claimed.

Abstract: An interrupt rate limiter limits the rate of interrupt signals being transmitted from a first node to a second node of a computer system. In certain implementations, a first logic block compares an accumulator value to a threshold value to determine whether to (i) block an interrupt signal received from the first node from reaching the second node or (ii) allow the interrupt signal to reach the second node, an accumulator register stores the accumulator value, which is (i) increased whenever the first logic block allows an interrupt signal to reach the second node and (ii) otherwise periodically decreased, a summation node receives the accumulator value and one or more values that determine whether the accumulator value is to be increased or decreased, and a second logic block determines whether to increase or decrease the accumulator value based on whether an interrupt signal has been transmitted to the second processor.

Abstract: A circuitry applied to an electronic device having a Universal Serial Bus (USB) type-C connector is provided. The circuitry includes a transceiver circuit, a physical layer circuit and a processing circuit. In operations of the circuitry, the transceiver circuit is coupled to the USB type-C connector. The physical layer circuit is configured to directly utilize a plurality of first signals from the USB type-C connector as at least one portion of Ethernet signals, and process the first signals to generate a plurality of processed first signals. The processing circuit is configured to process the processed first signals to generate an output signal.

Abstract: A USB integrated circuit includes three TX connecting component pairs and three RX connecting component pairs. The first TX connecting component pair and the first RX connecting component pair are respectively coupled to the first TX pin pair and the first RX pin pair of the first USB connector. The second TX connecting component pair and the second RX connecting component pair are respectively coupled to the first TX pin pair and the first RX pin pair of a second USB connector. The third TX connecting component pair is coupled to the second TX pin pair of the first USB connector or to the second TX pin pair of the second USB connector. The third RX connecting component pair is coupled to the second RX pin pair of the first USB connector or to the second RX pin pair of the second USB connector.

Abstract: An information handling system may include at least one processor; a first and a second backplane, wherein the first and second backplanes are Peripheral Component Interconnect Express (PCIe) backplanes; and a physical storage resource. The physical storage resource may be coupled to the at least one processor via a first port of the physical storage resource and via the first backplane, and the physical storage resource may be further coupled to the at least one processor via a second port of the physical storage resource and via the second backplane.

Abstract: Systems and methods for interfacing an application circuit to an industrial network include first and second interfaces, one or more controllers, and one or more memory devices. The one or more memory devices store instructions, which when executed, cause the controllers perform operations to convert messages between a specified message format according to a protocol of the industrial network and a protocol agnostic format.

Abstract: The present disclosure generally relates to reducing time for interface transmitter training based upon an assumed identify of the training partner. It is unlikely for a drive PHY to link up with multiple PHYs per power cycle. Therefore, it is a fair assumption that when there is no power loss, the drive PHY is connected to the same host device. The drive can therefore change its behavior based on the assumed identity of the host from previously exchanged identify frames, if the previously used training algorithm was sufficient for interface transmitter training for the particular host. The drive will go directly to the correct training algorithm without the need to do a PHY reset using a training algorithm that is tailored to the host and thus reduce interface transmitter training time.

Abstract: Techniques for implementing and/or operating an apparatus, which includes a host system, a memory system, and a shared memory bus. The memory system includes a first memory type that is subject to a first memory type-specific timing constraint and a second memory type that is subject to a second memory type-specific timing constraint. Additionally, the shared memory bus is shared by the first memory type and the second memory type. Furthermore, the apparatus utilizes a first time period to communicate with the first memory type via the shared memory bus at least in part by enforcing the first memory type-specific timing constraint during the first time period and utilizes a second time period to communicate with the second memory type via the shared memory bus at least in part by enforcing the second memory type-specific timing constraint during the second time period.

Abstract: A computer includes a processor, a PCIe-compatible interface bus that includes a root that is connected to the processor, and a routing complex that is connected to the root and is controlled by the processor. The computer also includes a first interface slot that is connectable to the root by the switches, a second interface slot that is connectable to the root by the switches, and an extended interface slot that is connectable to the root by the switches. The switches are configured based on properties of a first peripheral device to define a first switching configuration when the first peripheral device is connected only to the first interface slot and to define a second switching configuration when the first peripheral device is connected to both of the first interface slot and the extended interface slot.

Abstract: Systems, methods, and apparatus provide a multi-master serial peripheral interface. An apparatus is coupled to master and slave devices through an interconnect circuit using individual point-to-point SPI links. The interconnect circuit may be configured to couple pairs of devices selected from the plurality of devices through their individual point-to-point SPI links, enable a first transaction to be completed between a first pair of devices after a first master device in the first pair of devices initiates the first transaction, enable a second transaction to be completed between a second pair of devices after a second master device in the second pair of devices initiates the second transaction, and prevent a collision between the first master device and the second master device while the first pair of devices are engaged in the first transaction. The pairs of devices may be selected when they are participants in one or more transactions.

Abstract: In a method for the emergency shutdown of a bus system, and a bus system, having a master module and bus subscribers disposed in series, the master module and the bus subscribers sending data packets to one another with the aid of a data line, the method has the temporally consecutive method steps: in a first method step, a bus subscriber and/or the master module detect(s) an error status, in a second method step, the bus subscriber and/or the master module send(s) an emergency signal to all bus subscribers and to the master module, in a third method step, a further bus subscriber receives the emergency signal, immediately forwards it to an adjacent bus subscriber and simultaneously evaluates it, and in a fourth method step, the further bus subscriber shuts itself down automatically.

Abstract: A method for identifying bus nodes in a bus system makes it possible to be able to operate bus slaves of two different types in mixed systems. The detection of which bus slave has not yet been allocated an address in an addressing phase is carried out differently depending on a type of the bus slave. In all cases, however, the bus slave connected to the bus line farthest away from the bus master is identified as that bus slave to which an address is to be allocated.

Abstract: A front adapter for connecting to a control device, has a connection device connected to a predetermined system cable for connecting at least one field component, at least one wireless communication interface for wirelessly transmitting and receiving signals to or from at least one wireless one transmitting and/or receiving device which can be connected to a first field unit, and/or at least one bus-capable communication interface for transmitting and receiving signals via a signal bus to or from at least one bus-capable transmitting and/or receiving device which can be connected to a second field device, and a control and/or evaluation device which is adapted to control the transmitting of signals between the control device and the at least one wireless transmitting and/or receiving device and/or the at least one bus-capable transmitting and/or receiving device.

Abstract: A method for performing detection control of a write protection function of a memory device, an associated control chip, and an associated electronic device are provided. The method includes: detecting whether the memory device supports a first protocol to generate an interface detection result; detecting whether a write protection switch of the memory device is turned on to generate a write protection detection result; and according to the interface detection result and the write protection detection result, selectively initializing a transmission interface of a control chip as a first transmission interface conforming to the first protocol or a second transmission interface, to allow a host device to access the memory device through the control chip, wherein the first transmission interface corresponds to a first configuration of the control chip, and the second transmission interface corresponds to a second configuration of the control chip.

Abstract: Systems and methods are disclosed to perform a function level reset in a memory controller, in accordance with certain embodiments of the present disclosure. In some embodiments, an apparatus may comprise a storage controller circuit configured to receive a function reset indicator from a host device, the function reset indicator identifying a selected storage controller function executing at a storage controller of the apparatus. The circuit may abort each command associated with the selected function and pending at the apparatus based on the function reset indicator, verify that no commands associated with the selected function remain pending at the apparatus, and clear registers associated with the selected function based on the determination that no commands associated with the selected function remain.

Abstract: Aspects of the present disclosure relate to internet of things (IoT) device management. A first set of sensor data can be received from a first IoT device within an IoT sensor network, the IoT sensor network containing a plurality of IoT devices, wherein a subset of the plurality of IoT devices within the IoT sensor network are in an inactive state. The first set of sensor data can be analyzed to determine whether an activation condition is satisfied. In response to determining that the activation condition is satisfied, a second IoT device within the subset can be activated, wherein activation leads to collection of a second set of sensor data from the second IoT device.

Abstract: A port adaptation method applied to a network device including a port adaptation apparatus includes probing whether the first port and the second port are connected to power sourcing equipment, and maintaining or changing one of the first port and the second port that is connected to power sourcing equipment as, or to, a powered state, and a state of the other port as, or to, a powering state.

Abstract: The subject technology provides for managing a data storage system. Commands are identified into as a first command type or a second command type. The commands identified as the first command type are assigned to a first queue, and the commands identified as the second command type are assigned to a second queue. After the commands from the first queue and the commands from the second queue are processed based on a scheduling ratio over a predetermined period of time, a write amplification factor, number of host read commands, and number of host write commands during the predetermined period of time are determined. The scheduling ratio is updated based on the write amplification, the number of host read commands, the number of host write commands, and a predetermined scheduling ratio factor. Subsequent commands are processed from the first queue and the second queue based on the updated scheduling ratio.