Abstract: Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array.

Abstract: A communication controller, a method and a node agent is disclosed, The communication controller comprising: a data transmission port configured to be connected to corresponding logical channels; an application port configured to provide data to or from corresponding applications; a node agent having node control data comprising at least one trained machine learning model, configured to: monitor performance characteristics for data inflow to a data transmission port; monitor an at least one local observable; control the connection between the data transmission port and another data transmission port causing outflow of data, or between the data transmission port and the application port, causing inflow of data if the application port receives data, and outflow of data if the application port sends data; control the connection between the transmission ports and the application ports based on the monitored performance characteristics, the at least one local observable, the at least one trained machine learning m

Abstract: The present invention is directed to a system and method that utilizes a central repository for storing and sharing Thing Description (TD) Documents with USB extensions that correspond to specific USB I/O schema. A Network Interface Module uses the USB I/O vendor and product identifications to query the central repository and download the appropriate Thing Description (TD) document for the specific USB I/O device. The Network Interface Module parses the TD document and builds the appropriate Web of Things (WoT) data architecture that establishes the interface between the network and the USB I/O device thereby allowing the USB I/O device to become an IoT device.

Abstract: There is provided an information processing system to increase a speed of returning identification information in response to a received command in the case where an identification information requesting command is received, the information processing system including: a plurality of processing devices each of which includes a storage unit configured to store an identification information piece; a management device configured to acquire the identification information piece from each of the plurality of the processing devices; and a communication device configured to communicate with an external device. The management device writes the identification information piece acquired from each of the plurality of the processing devices into the communication device.

Abstract: A system for detecting HDDs and in-position states of each of them includes an HDD controller, an analysis module, and a BMC chip. The HDD controller is electrically connected to the HDDs for obtaining SGPIO information and outputting testing signals comprising the SGPIO information. The analysis module receives the testing signals and generates in-position state information according to voltage levels of the testing signals. The BMC chip is electrically connected to the analysis module. The BMC chip receives the in-position state information from the analysis module and generates a detection log accordingly.

Abstract: Disclosed herein is a method and Serially Attached SCSI (SAS) controller for transmitting data using SCSI. In an embodiment, a plurality of I/O operations received from a storage unit are fragmented into a plurality of blocks. Further, each of the plurality of blocks are mapped with corresponding memory drives. Thereafter, a reduced number of virtual lanes required for transmitting the plurality of blocks to the corresponding memory drives is estimated. Finally, the reduced number of virtual lanes are created for transmitting the plurality of blocks to the corresponding memory drives. In an embodiment, the present disclosure uses virtual lanes for transmitting data, thereby eliminating requirement of dedicated, physical lanes for transmitting the data. Consequently, according to embodiments of present disclosure, the SAS controller may be configured to simultaneously activate multiple virtual lanes for completing the data transmission, thereby resulting in faster and reliable data transmission.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an interface. The interface may be configured to detect a hot unplug condition based on a first output voltage at an output terminal of a first buffer circuit and a second output voltage at an output terminal of a second buffer circuit, wherein the first and second buffer circuits receive a common input. The interface may further detect the hot unplug condition based on a difference of a peak magnitude of the first output voltage and a peak magnitude of the second output voltage.

Abstract: A data processing pipeline controller receives a request, from a data iterator associated with a machine learning model, for a data output of a module in the data processing pipeline, wherein each module in the data processing pipeline has an associated cache. The controller determines whether a data output of the module is stored in the associated cache and responsive to the data output being stored in the associated cache, provides the data output from the associated cache to the data iterator without processing data through the module.

Abstract: One embodiment includes a computing device including peripheral component bus interfaces for connection to a peripheral component bus, a first integrated circuit (IC) chip comprising a processor to initiate a register setup process of the device, a second IC chip including a tile processor including multiple tiles, each tile including at least a processing core configured to generate requests to at least one of the peripheral component bus interfaces, steering configuration registers to store steering configuration data, and steering logic to steer the generated requests responsively to the steering configuration data in the steering configuration registers, and steering register setup circuitry including a multicaster and a register setup memory, wherein the processor is configured to write the steering configuration data to the register setup memory, and the multicaster is configured to multicast the steering configuration data written to the register setup memory to the steering configuration registers of

Abstract: An integrated circuit for monitoring components of the integrated circuit, comprising: a resource monitoring circuit configured to: track activity factors for a plurality of components of the integrated circuit; evaluate the activity factors for each of the plurality of components; determine whether an activity factor for a particular component of the plurality of components exceeds a threshold; and transmit, from the resource monitoring circuit, a signal to a software element, causing the software element to deactivate the particular component and activate an alternate component, when the activity factor for the particular component exceeds the threshold and the alternate component is available to substitute for the particular component.

Abstract: Extended message signaled interrupts (MSI) data are disclosed. In one aspect, MSI bits are modified to include a system level identifier. In an exemplary aspect, an upper sixteen bits of the MSI message data are modified to be the system level identifier. By providing the system level identifier within the MSI message data, an interrupt controller can verify the interrupt source.

Abstract: The present invention provides a graphics processing system, the graphics processing system comprises a central processing unit, a plurality of graphics processing units, a bus communication protocol switch and a management board. The graphics processor units are communicatively coupled to the central processing unit. The bus communication protocol switch is coupled to the graphics processing units to implement mutual communications between the graphics processor units. The management board is coupled to the bus communication protocol switch for managing the bus communication protocol switch. The bus bar communication protocol switch can maximize and equalize the peer-to-peer network communication bandwidth between the graphics processing units, and the theoretical maximum bidirectional bandwidth can reach 300 GB/s, and is capable of expanding additional eight-graphics processing units to form a sixteen-GPUs system that enables peer-to-peer network communication of any two graphics processing units.

Abstract: The present disclosure relates to a system and related methods, apparatuses, and computer program products for controlling operation of a device based on a read request. For example, a method for performing an operation in response to a read request may include a first computing device receiving a request to read a value sent to the first computing device by a second computing device via a wireless communication link between the first and second computing devices. The method may further include the first computing device determining an operation corresponding to the value. The method may additionally include the first computing device performing the operation corresponding to the value in response to the request.

Abstract: A system that allows access to a virtualized device is disclosed. The system may include a device, a processor, and a communication unit coupled to the device via a communication link. The device may include hardware resources configured to be shared by multiple threads executing on the processor. The communication unit may be configured to detect a request to access the device by the processor. In response to the detection of the request, the communication unit may send one or more instructions to the device via the communication link using a communication protocol.

Abstract: The current document is directed to a family of integrated hardware controllers that provides for cost-effective, high-bandwidth, and scalable incorporation of SSDs into large, distributed-computer systems. Certain implementations of the integrated hardware controller include dual media-access controllers for connection to one or more local area networks, remote-direct-memory-access (“RDMA”) controllers for supporting RDMA protocols over the local area network, an NVMe controller that provides access to an SSD. In certain integrated-hardware-controller implementations, the RDMA and NVMe controllers are implemented in one of a field programmable gate array (“FPGA”) and application-specific integrated circuit (“ASIC”).

Abstract: An apparatus and method for controlling a virtualized endpoint device are disclosed. A processor may be configured to execute instructions included in multiple execution threads. A first device may be configured to perform multiple command and data functions, and a communication unit may include a first port coupled to the first device via a first link and be configured to send instructions from the processor to the first device via the first link using a first communication protocol. The processor may be further configured to execute first and second sets of commands included in respective execution threads. The first set of commands may be associated with the plurality of command functions and the second set of commands may be associated with the plurality of data functions.

Abstract: A high speed intelligent network recorder for recording a plurality of flows of network data packets into and out of a computer network over a relevant data time window is disclosed. The high speed intelligent network recorder includes a printed circuit board; a high speed network switching device mounted to the printed circuit board; and an X column by Y row array of a plurality of intelligent hard drives with micro-computers mounted to the printed circuit board and coupled in parallel with the high speed network switching device.

Abstract: A system and method for management of data and power of a data acquisition device may include a power and storage module (PSM) comprising a memory and a power source unit, the PSM adapted to provide power to a data acquisition portable device (DAPD) and to store data received from the DAPD and a docking unit adapted to charge the power source unit and to perform at least one of: reading information from the memory and writing information to the memory. Charging the power source unit and transferring data to/from the memory may be done substantially at the same time and by the same docking unit.

Abstract: An apparatus and method for controlling a device with shared hardware resources to provide separate execution environments for control and data functions are disclosed. A processor may be configured to generate a first request to access control functions of the device in response to execution of a first thread, and generate a second request to access data functions of the device in response to execution of a second thread. A communication unit may send first indicative of the first request and second data indicative of the second request to the device via first and second ports, respectively.

Abstract: Interference cancellation in a receiver can be used to improve bandwidth efficiency. The transmission of bursts from different terminals scheduled at separate time intervals can overlap partially such that time used for information transmission is optimized. For example, a receiver includes a signal processor including instructions executable to select first data including a first burst and a successive second burst from a transmission. The signal processor demodulates and decodes information from the first burst. The signal processor further generates a remodulated first burst based on recoded and remodulated information and generates second data by subtracting the remodulated first burst from the first data. The signal processor synchronizes with a stored symbol pattern in the second burst; and demodulates and decodes the information from the second burst. With such arrangement, the performance of each link is not affected by the partially overlapping burst.