Abstract: A keyboard/display apparatus enters tabular data in two different modes. For the entry of tabular data in a row by row mode, a tab key on the keyboard is depressed for causing tabbing to a next set tab on the same line. For the entry of tabular data in a column by column mode, a coded tab is keyed for causing left tabbing to a nearest set tab on a following line.

Abstract: A data processing system includes three resources, i.e., a memory, a general purpose register file having a plurality of elements and a stack having a top. The system further includes a first mechanism for making the top of the stack correspond to at least one of the elements in the general purpose register and a second mechanism for controlling the operation of the stack. When the element to which the top of the stack corresponds is specified in an instruction register of the system, the top of the stack is selected to be accessed by the first mechanism and the operation of the stack is controlled by the second mechanism.

Abstract: A combination of one or more shift registers with a binary counter and a memory device is disclosed wherein binary information inputs are supplied to the shift register through a plurality of AND gates which also receive inputs from a pulse generator and the output of the shift register is supplied through a second plurality of AND gates to a storage device, and wherein the binary counter supplies inputs to the second plurality of AND gates, and wherein the pulse generator supplies outputs to the shift register, the binary counter and to the first plurality of AND gates. A second embodiment provides a plurality of shift registers which receive outputs from the first shift register and are connected to a plurality of memories through additional AND gates which are controlled by the pulse generator and the associated shift register.

Abstract: A fast synonym detection and handling mechanism is disclosed for a cache directory utilizing virtual addressing in data processing systems. The cache directory is divided into 2.sup.N groups of classes, in which N is the number of cache address bits derived from a translatable part of a requested logical address. The cache address is derived from a non-translatable part of the logical address which is used to simultaneously select one class in each of the 2.sup.N groups. The selected class entries are simultaneously compared with one or more dynamic lookaside address translator (DLAT) translated absolute addresses. Compare signals, one for each class entry per DLAT absolute address, are routed to a synonym detection circuit. The detection circuit simultaneously interprets all directory compare signals and determines if a principle hit, synonym hit or a miss occurred in the cache for each request.

Abstract: A computer system architecture includes a processor for processing data, a memory for storing at least macroinstructions for use by the processor, microinstruction logic for storing and providing sequences of frequently used microinstructions, and busses for transmitting at least macroinstructions between the processor and memory. Microinstruction memory circuitry stores microinstructions in segmented form in available microinstruction memory space. Microinstruction segment by segment selection circuitry effects the selection of successive microinstructions of sequences of microinstructions.

Abstract: A portable electronic dictionary and language interpreter comprises an input device for simultaneously entering at least two different words in a first language, a translator for causing retrieval for equivalents for the at least two different words, and a voice synthesizer for speaking the at least two different words in the first language in the form of synthesized sounds, respectively. The pronouncing of both or either of the at least two different words in the first language can be selectively repeated in response to an actuation of a repeat key switch. The translated word or words now indicated in a display can be replaced by the input word or words once indicated in the same display.

Abstract: A control system for a plurality of I/O apparatuses used for transferring data between a main memory and an I/O apparatus controlling device through a channel control device. If an error occurs in the data transfer, no response signal is sent to the I/O apparatus controlling device from the channel control device and the absence of the response signal is detected by time supervision in the supervising circuit in the I/O apparatus controlling device, so that only the portion of the I/O apparatus related to the error is stopped.

Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, data storage array, a decimal arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc., and to accommodate these different uses the output decoder is mask-programmable. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.

Abstract: Internal states of storage devices within a digital data processing system are made accessible using variable mode multi-bit shift register storage devices. The inputs and outputs of these shift register storage devices are interconnected by gating means which may be selectably controlled to form separately selectable serial strings along which the bits of a selected string may be caused to be shifted to a monitoring unit for monitoring, diagnosing and/or correcting purposes and then returned, via the string, to their original locations in the shift register storage devices, after which normal data processing operations can be resumed, or other appropriate action taken.

Abstract: A data processor architecture wherein the processors recognize two basic types of objects, an object being a representation of related information maintained in a contiguously-addresed set of memory locations. The first type of object contains ordinary data, such as characters, integers, reals, etc. The second type of object contains a list of access descriptors. Each access descriptor provides information for locating and defining the extent of access to an object associated with that access descriptor. The processors recognize complex objects that are combinations of objects of the basic types. One such complex object (a context) defines an environment for execution of objects accessible to a given instance of a procedural operation. The dispatching of tasks to the processors is accomplished by hardware-controlled queuing mechanisms (dispatching-port objects) which allow multiple sets of processors to serve multiple, but independent sets of tasks.

Abstract: An electrically programmable and erasable ROM (EPROM) is accessed via a selector and an address counter, all mounted on a PC board which includes also a regular VCC bus. The EPROM output lines feed an output circuit, parts of which may be on other boards. The board, however, has additional terminals connected to the EPROM output lines in addition to a protective circuit limiting the voltage level in the output circuit in case high reprogramming signals are applied by an external unit to some of these additional terminals for programming via the EPROM output terminal. One of the latter terminals connects to the VCC input of the EPROM and a Schottky diode connects the VCC bus to that input to protect the latter bus from a higher-than-normal supply voltage needed during reprogramming.

Abstract: In a data processing system, a central subsystem includes a plurality of special purpose processing units with one of the processing units serving as a control processing unit within a central subsystem. The processing units are coupled to a common subsystem bus for the transfer of data, control information, and address information within the central subsystem. Access to the subsystem bus is allocated by a bus control unit which also interfaces the central subsystem with other processing units such as a system memory or system I/O devices that are included in the data processing system.

Abstract: The internal states of one or more micro-code storing RAMs (random access memories) which control program flow in a digital data processor are made accessible for loading, changing or monitoring purposes using variable mode multi-bit shift register storage devices for the input-output register of each RAM. When the contents of a selected location in a RAM is to be monitored, changed or loaded, the data stored in the selected location is read into the RAM's input-output register and the interconnections of the corresponding storage devices are reconfigured to form a serial string along which the bits in the string are shifted to a monitoring unit for monitoring, diagnosing, changing and/or loading purposes and then returned, via the string, to their original locations in the RAM's input-output register. If changes are required, the changed bits returned to the RAM's input-output register are written into the selected location in the RAM before normal operations are resumed.

Abstract: An error display circuit in a data processing device containing an independent processor circuit is set by an initializing signal generated when a power source is turned on and reset by the operation of the processor circuit when the initializing signal is removed. By this means the fact that the processor circuit can operate normally at a level above a definite degree can be affirmed by the state of the display circuit.

Abstract: A microprogrammed data processing system includes a cache memory, a decimal unit and an execution unit. The decimal unit receives operands from cache memory, strips the non-decimal digit information from the operands, and assembles the 4-bit decimal digits from the operand into words containing a maximum of 8 decimal digits for transfer to the execution unit. The execution unit processes the words in accordance with a decimal numeric instruction. The throughput of the system is increased when processing short operands which contain 15 decimal digits or less by apparatus in the decimal unit which detects the short operand and determines the number of cache memory cycles between the cycle the first word of the short operand is received from cache memory and the cycle on which the first assembled word is transferred to the execution unit for processing.

Abstract: A signal processor has a single random access memory having a capacity equal to or greater than the total number of words in a processing interval. An address sequence mechanism is operatively connected to the memory for addressing the memory in a sequence for, after the first processing interval, reading out data for the first processing interval continuously in a preselected output order and overwriting data for the next processing interval continuously in a preselected input order in the locations of the data being read out. An address checker is connected to the address sequence mechanism for checking the addresses thereof for error and a controller is operatively connected to the address sequence mechanism, address checker, and memory for controlling their operation.

Abstract: A transaction execution system is provided in which key initiated transaction requests at a terminal remote from and in communication with a host data processing system are processed at the terminal under the selective control of the host. Each active transaction key at the terminal keyboard is assigned one of three different states by a financial institution table. The table provides keyboard customization by selecting one of a plurality of different groups of key states for the different keys arrived at by combining the key states in a custom key set table with the states in a base key set table in response to information from a credit card entered by a consumer. Transactions requested by keys assigned a standard state are processed at the terminal without further data input being required of the consumer.

Abstract: In a central dictation system of the type having a plurality of recorders, a plurality of dictate stations are adapted to seize individual ones of the recorders, and a plurality of transcribe stations assignable to transcribe the dictated messages, a display device displays information identifying predetermined parameters related to the messages being recorded, including the status of such messages, immediately following the seizure of respective recorders by corresponding dictate stations, whereupon messages are dictated onto such recorders. The display device displays information associated with respective messages in corresponding lines, the displayed lines being segregated into areas as a function of the particular status of the associated messages. Depending upon a change in the status of an associated message, the line of displayed information may be transferred from one segregated area to another.

Abstract: A communications device transfers process data between a data processing system and an external device at high speed. The communications device receives command signals from a user process program in the data processing system and from the external device. The communications device generates physical addresses in the data processing system with respect to which process data is to be transferred, the physical addresses being generated in response to virtual addresses supplied in the commands. The communications device and the external device also each include apparatus for signalling the other that data is being transferred at too rapid a rate to be processed, or that data is temporarily not being transferred, to prevent data being lost and an error being sent to the data processing system.

Abstract: In a computer output microfilmer (COM) comprising a computer output read out device having a magnetic recording tape, a central processor unit, and a recording unit, the computer output read-out device is provided with a buffer storage and a data processing device. The data read out from the magnetic recording tape are stored in the buffer storage and read out therefrom under the control of the data processing device. Thereby, the steps of reading out the data of page (N+2) from the magnetic recording tape, processing the data of page (N+1) in the central processor unit, and recording the data of page (N) in the recording unit are conducted in parallel.