Abstract: A modular read-write and read-only memory unit capable of employing both direct and indirect decimal and symbolic addressing, a central processing unit capable of performing both serial binary and parallel binary-coded-decimal direct and indirect memory register arithmetic, and an input-output control unit capable of bidirectionally transferring information between the central processing unit and a number of input and output units are controlled by a microprocessor included in the central processing unit. The input and output units include a keyboard input unit, a magnetic card reading and recording unit capable of bidirectionally transferring information between an external magnetic card and the read-write memory unit, and a solid state output display unit capable of displaying three lines of numeric information.

Abstract: An intersystem communication control system in an intersystem link (ISL) unit is provided to accommodate the simultaneous bidirectional transfer of binary coded information between communication busses in a data processing system, wherein the plural communication busses are electrically interconnected by ISL unit twins, and information may be transferred between plural communication busses asynchronously.

Abstract: A programmable electronic calculator is disclosed for numerical evaluation of mathematical problems through application of one or more basic mathematical operators, properly grouped, to each input numerical operand of a mathematical problem according to the accepted rules of mathematical combinations. One may select any numerical operand, any of the four basic arithmetic operators, left parenthesis and right parenthesis to denote groupings, a storage register for receiving a numerical operand to be used in computation or a numerical operand representing a result of a partial or final computation, or a storage register whose contents it is desired to print. Entry of each numerical operand and mathematical operator is accompanied by a printed record of that numerical operand and that mathematical operator so that the mathematical problem may be continually monitored as it is being entered. Depression of an equals key is followed by evaluation of previously designated operations and printing of the result.

Abstract: A switching arrangement is disclosed which permits storage devices to be shared by two separate controllers, each controller in turn receives commands and transfers the stored data to a different data processing system. The arrangement involves a plurality of subchannels, each of which comprises at least one addressable storage device and two addressable interlocked port switches, each of which functions to connect one side of the subchannel and the device to one of the controllers. The subchannel switching arrangement is characterized by each switch being addressable as if it were another device, which permits the port switches to be implemented with minimal changes to either the controller or the device.

Abstract: An improved memory addressing system is incorporated in an electronic calculator having input keys for entering numerical data, operational instructions and memory control instructions, a memory for storing the numerical data, and a processor for executing the operational instructions and memory control instructions with numerical data transferred to or from the memory. The keys may be operated in a specific sequence that designates an area in the memory comprising a plurality of memory addresses. A detector detects actuation of the keys in the specific sequence and generates an output signal indicative thereof. A memory access control then sequentially accesses all of the addresses in the memory area in response to the output signal.

Abstract: A time base converter for compressing or expanding the time base of an input digital signal comprises a data input terminal; a digital output circuit; a number n of memory banks for storing the input digital signal which is written therein at a write clock frequency and read out therefrom at a read clock frequency, and having a memory cycle with a writing phase and a reading phase in each period thereof and which is synchronized with the read clock, with the write clock frequency and the read clock frequency being different from one another; a number M of input latches in series between the data input terminal and each respective memory bank for gating to the latter a group of data words of the input digital signal in parallel, each input latch having a number N of channels, each channel processing a predetermined subgroup of the group of words; and an output latching circuit to couple the memory banks to the output circuit.

Abstract: A system is provided in which a memory is divided into two parts, so that a substantially continuous printing operation can be carried out by reading information to be printed from one part of the memory, with printing being interrupted for brief periods of time to permit writing of information in the other part of the memory. The writing into the memory is done on an alternate line basis, with the omitted lines being filled during a subsequent write operation so as to convert the interlace input to a standard format. At an appropriate time, the two parts of the memory are switched so that the read-out for the printing is carried out from the part into which information has just been written, and the writing takes place in the part of the memory which has been cleared during the preceding read operation.

Abstract: A dynamic address translation unit for converting virtual or "logical" address values into real or "physical" address values. A translation Lookaside Buffer (TLB) stores physical addresses corresponding to a limited number of previously translated logical addresses. The available space in the TLB is divided into partitions, each of which stores address translation data for a particular user process. The TLB partition in current use is identified by the value stored in a user partition counter, which is also used to verify that certain process control information (stored in a stack memory location) associated with the partition matches the process control information for that user process which is currently in control of the central processing unit.

Abstract: Within an electrophotographic copying machine having a predetermined number of sensing elements each deriving an output indicative of respective one of operating states of the machine, there is provided a single chip, MOS-LSI microprocessor responsive to the outputs of the sensing elements to control the machine in a sequential or serial mode.

Abstract: Cyclic instrument control and data acquisition functions which are critically dependent upon synchrony are directed from a computer based system including a FIFO buffer adapted to feedback the most recently active word from its output register and re-store said word at a corresponding sequential position in the FIFO queue. To accommodate complex and interleaved control and data acquisition cycles, each FIFO word has a state portion for commanding external devices, a persistence portion for specifying the duration of a selected state active in the FIFO output buffer for a desired persistence interval, and a repetition portion for specifying the number of consecutive discrete repetitions of the currently active state-persistence datum at the output of the FIFO. Termination of the repetitions of the cyclic sequence is accomplished at the expiration of a preselected number of complete cycles.

Abstract: Apparatus which detects and corrects both transient and single bit memory read errors while selectively logging only solid (that is, hardware-related) single bit memory read errors. Each of a plurality of memory modules directly transmits uncorrected memory data to a processor memory control while also providing for automatic local restoring of corrected data back into the memory address which produced the single bit error. The processor memory control provides its own error detection and correction employing syndrome generating and decoding circuitry which detects both multiple and single bit errors. Multiple bit errors are not corrected, but merely brought to the attention of the processor. Single bit errors are corrected, but only those which are found to most likely be solid errors are logged. A solid single bit error is recognized by detecting when two single bit errors having the same memory address occur consecutively.

Abstract: A digital input apparatus is provided which is used as an input apparatus for a digital signal processor and can eliminate noise components resulting from electromagnetic induction and resulting from chattering which is produced by the opening or closing of a contact. One input signal outputted from the multiplexer (105) is applied through a latch flip-flop (108) to a counter (114) used on a time sharing basis so that counting is effected. Individual counts corresponding to a plurality of input signals are stored in a memory (117). When a count becomes all "1's" or "0's", the counter (114) produces a carry signal or a borrow signal supplied to a J-K flip-flop (113). The J-K flip-flop (113) produces an input signal of a predetermined waveform free from noise components.

Abstract: A computer having a programmable network assumes specialized operating configurations corresponding to the functions to be executed at each cycle. For such a computer, the program consists of the description of a Finite State Machine (FSM) that performs the desired process. The language for describing these FSMs consists of digital words formed with a grammar similar to that of spoken languages. This language is equally well suited for expressing the processes that the user has in mind and for actually controlling the computer, thus making the compiler unnecessary. The data related to each FSM are organized in the form of pages that circulates between the registers of the programmable network and a memory that configurates itself as the data, thus making the burden of addressing unnecessary.

Abstract: A read only memory apparatus for use in a byte oriented processor (10) includes a data selector (25) which responds to the first memory fetch of a memory reference instruction (40, 28) to provide a selected set of output bits (20) from a read only memory to a particular portion (22) of the processor data bus. The apparatus provides a set of replacement bits (26) to the same portion of the data bus (22) in response to each occurrence of detection (29, 30') of the most significant byte of a such memory reference instruction being provided to the data bus. The replacement bits occur in the most significant byte of the address referred to in the memory reference instruction and prevents the processor's program counter from jumping out of the address space alloted to the read only memory. In the preferred form, the same set of switches (17) used with an address decoder (15) to define the location of the ROM circuit in the address space of the processor's memory also provides replacement bits.

Abstract: An information transfer system is described that includes a central processing unit (CPU) interconnected with a peripheral device such as an operator console by an interface bus of finite capacity. Transfer of information in the system is normally in a preferred direction from the CPU to the console. Provision is made to transfer information concerning key depressions on the console from the console to the CPU without using the bus by utilizing a normally continuously operating counter in the CPU that provides a sequence of coded count signals representative of individual keys that are provided on the console and that may be depressed. A comparator in the console compares coded count signals from the CPU counter with coded signals from the console representative of actual key depressions and provides a stop signal to the CPU counter via a single control line when an equal compare of the CPU counter and console coded signals occurs.

Abstract: A logic state analyzer stores into a data acquisition memory only state data meeting preselected qualification state criteria chosen to weed out state data not of interest among the totality of states occuring within a collection of digital signals. The data acquisition memory retains only the last m-many states stored therein. A selectable integer k, o.ltoreq.k.ltoreq.m, determines how many additional storage operations are performed for qualified state data following the detection of a preselected trigger condition. The actual number of states occurring in the collection of digital signals after the trigger condition but before the storage of the kth qualified data state can be many times the value of k. Qualifying the state data prior to storage allows a modest size data acquisition memory to do the work of a much larger memory and spares the user the task of sorting through much state data known not to be of interest.

Abstract: A peripheral device address assignment mechanism is described which does not require the use of plugboards or jumpers. This mechanism enables a host processor to select any desired peripheral device and set its device address to any desired value at any desired time. This is accomplished by providing each peripheral device control unit with a loadable device address register for holding the device address assigned to its peripheral device. Each device control unit is further provided with circuitry responsive to the appearance of a unique I/O command on the processor I/O bus and to the activation of a unique set of the I/O bus data lines by the processor for loading into its device address register the desired device address value as supplied thereto by the processor via the I/O bus.

Abstract: A peripheral-controller, designated as a Train Printer-Data Link Processor, provides the control interface between a main host computer and a train printer mechanism. A plurality of such peripheral-controllers make up an I/O subsystem whereby a main host computer is relieved of housekeeping duties in regard to peripheral units. This train printer data link processor (peripheral-controller) is made up of two slide-in circuit cards. The first card, known as the common front end (CFE) provides micro-code word operators for data transfer and printing operations in addition to supplying a specialized RAM buffer memory for storing data words from the main memory of the main host computer and selecting these words for printing in the attached peripheral device known as a train printer mechanism.

Abstract: Apparatus which detects and corrects both transient and single bit memory read errors while selectively logging only solid (that is, hardware-related) single bit memory read errors. Each of a plurality of memory modules directly transmits uncorrected memory data to a processor memory control while also providing for automatic local restoring of corrected data back into the memory address which produced the single bit error. The processor memory control provides its own error detection and correction which detects both multiple and single bit errors. Multiple bit errors are not corrected, but are merely brought to the attention of the processor. Single bit errors are corrected but only those which are found to most likely be solid errors are logged. A solid single bit error is recognized by detecting when two single bit errors having the same memory address occur consecutively.

Abstract: An integrated circuit data processor arrangement is provided having a data processor architecture that can be implemented entirely of integrated circuits. The combination of an integrated circuit read only memory and an integrated circuit alterable memory and the ability to process operands stored in the alterable memory under control of instructions stored in the read only memory facilitates a fully integrated circuit data processor. Other data processor features that facilitate the fully integrated circuit architecture include integrated circuit paging logic and a storing arrangement for storing information in the main memory. Systems applications of the integrated circuit computer includes control of machines, control of photo-optical devices, and interaction with an operator.