Abstract: Automatically updatable error logging means incorporated in a multi-phase, bit addressable, variable field memory system. The memory system is partitioned into a plurality of individually addressable memory stacks and employs time-shared accessing of the memory stacks along with time-shared error detection and correction which is used with the error logging means to provide for automatic logging of detected errors during memory accesses on a priority basis.

Abstract: A specialized RAM buffer memory is provided to work in conjunction with a peripheral-controller designated as a train printer-data link processor. The RAM buffer memory has addressable locations holding two 8-bit bytes at each addressable location. Thus, each addressable location has a top byte and a bottom byte, each of which represents a graphic character. A first dedicated portion of the buffer storage memory is called the print image buffer (PIB). This buffer is loaded with character data according to the number of print columns used in the train printer. When the print image buffer is loaded with character information, it constitutes one full line of print across the 132 columns. A second dedicated area of the memory buffer is called the train image buffer (TIB). This buffer is loaded with codes for the character set that matches the current print train module used in the train printer.

Abstract: An address generator for an M-interleaved memory for accessing row or column elements of a matrix stored in a skewed matrix pattern includes an apparatus for circularly shifting the addresses for the i.sup.th row of a matrix by s(i-1) positions so that both row and column elements of the matrix can be accessed at the same access rate. In other words, apparatus is provided for circularly generating the sequences of appropriate memory addresses for the desired row or column elements so that either the row or column elements can be accessed at the memory system's maximum access rate. The apparatus includes a base register having an input connected to a first adder which adds an input value A to the contents in the base register for storing the output of the adder as a pointer to the beginning of the current row of the matrix in the memory to be accessed.

Abstract: A logic control system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein an ISL unit may be reconfigured to reallocate communication bus resources without incurring excessive software overhead time losses.

Abstract: A bit-oriented data link controller provides the interface between a microcomputer or terminal and a data communications link. The data link controller is capable of accommodating the three most commonly available bit-oriented data link control protocols, namely SDLC, HDLC, and ADCCP. The data link controller provides the data communications interface for both primary and secondary stations in stand-alone, polling, and loop configurations.

Abstract: An adaptable programmable calculator is provided by employing a modular read-write and read-only memory unit capable of being expanded to provide the calculator with additional program and data storage functions oriented towards the environment of the user, a central processing unit capable of performing both serial binary and parallel binary-coded-decimal arithmetic, and an input-output control unit capable of bidirectionally transferring information between the memory or central processing units and a number of input and output units. The memory, central processor, and input-output control units are controlled by a microprocessor included in the central processing unit. Also the calculator may be operated manually by the user from an alphanumeric keyboard input unit or automatically by a program stored within the memory unit to perform calculations and provide an output indication of the results thereof. It may also be employed to load programs into the memory unit from the keyboard input unit.

Abstract: A memory controller couples to a bus and controls a number of memory module units or memory modules. The controller includes a number of queue circuits for processing a variety of different types of memory requests received from a number of command generating units coupled to the bus requiring the controller to operate in a corresponding number of different modes. The controller includes queue timing and control apparatus which couples to the modules and to the queue circuits for minimizing conflicts between the types of requests and the internal operations required to be performed by the controller.

Abstract: A memory controller coupled to a number of memory module units and includes a number of control circuits. The control circuits include address counter circuits which are loaded with a portion of the address of each predetermined type of command or memory request from a requesting device. This command when decoded causes the controller to read out from the memory module units a predetermined number of word pairs starting with the location specified by the stored address portion.

Abstract: An industrial control system is disclosed in which various on/off or other binary functions of an industrial process are each controlled by a separate single board computer. Each single board computer is provided with a simplified system whereby the user can interconnect a logic system between input ports and output ports of the computer to control the setting of the binary data at the output ports in accordance with the selected logic system in response to the data applied to the input ports with the output ports being connected to control the on/off and binary functions in the system. The logic functions are implemented in each single board computer by use of an applications program and a patch panel program. In the applications program, the system responds to input data in a flag memory and sets output flags in the flag memory in accordance with each possible logic function that might be used in the system.

Abstract: In an electronic accounting machine, a single line display shows both guiding messages entered by the programs of the machine and reply messages entered by an operator through a keyboard. The display is divided into a left part and a right part whose lengths are programmed by the machine. This latter enters a guiding message formed by a permanent part indicating the current work of the machine and a temporary part indicating the data required by the running program. These parts are displayed respectively on the left and the right part of the display. The keyboard reply message replaces the temporary part, whereby the reply message is displayed in the right part of the display simultaneously with the permanent part of the guiding message present on the left part.

Abstract: A communication system is provided for use in an electronic accounting system. The system includes a plurality of remote terminals for data entry, a serial data bus, a universal synchronous/asynchronous receiver/transmitter (USART), a priority interrupt controller and a processor connected to the bus to allow processor controlled bidirectional communication over the bus.

Abstract: A miniature computer has a main section which includes a central processor, a read only memory storing a monitor program, a random access memory for executing the monitor program and a controlling circuit for peripheral equipment, and a hand-held controller electrically connected to the main section through a flat cable, the hand-held controller having a keyboard and display device such that the keyboard has keys of numerals 0 to 9 and the alpha characters A to Z for enabling data in the form of symbolic language to be input according to an assembler program. The assembler program is stored in the read only memory and the symbolic language data is converted to corresponding machine language. The hand-held controller includes a key input system which utilizes encoders rather than mulitplexers to detect and transmit key input data data to the main section.

Abstract: In a data processing system a cache memory comprises level one and level two even and odd data stores and level one and level two even and odd directory stores. The directory stores include a plurality of storage locations for storing the most significant bits of the address numbers associated with the data words stored in the level one and level two even and odd data stores. The level one and level two even and odd directory stores are addressed by the least significant bits of the address numbers. Comparator circuits compare the high order bits of an address number supplied in a memory request to the high order bits stored in the level one even and odd directory stores at storage locations identified by both the low order bits of the address supplied in the memory request and the low order address bits incremented by one. A hit detector circuit determines whether one, both, or none of the requested words are stored in the cache memory by analyzing the outputs of the comparators.

Abstract: A malfunction preventing system for a microcomputer system is disclosed which detects an abnormal condition in the program execution to produce an alarm or reset signal to automatically restart the computer. The malfunction preventing system is applicable to automotive engine control wherein the computer is capable of returning to normal operation upon detecting a malfunction in program operation for fuel parameter calculation, thereby to keep the automotive engine control in order.

Abstract: A modified least recently used resolving network provides the capability of ignoring any one or more of the signals indicating use of the device in resolving the least recently used status of the devices.

Abstract: A computer system having a CPU connected to I/O devices via a channel sets addresses into the I/O devices by the CPU. The I/O devices, for purposes of control, are grouped in types. To load device addresses or identifiers, the processor sends a type identifier to the I/O devices. The device having the highest ordered priority of the same type of device and which does not have an assigned identifier responds by inhibiting all lower ordered devices of its type. It is then loaded with its unique assigned identifier which results in the setting of a status latch therein. This setting allows the next lowest ordered device of the same type of devices to then be assigned and loaded with an identifier by the processor. This process continues until all I/O devices of the same type are loaded with identifiers. The process is then repeated for each other type of I/O devices in the system.

Abstract: A control store included in a data processing system for storing microinstructions in a plurality of microinstructions storage locations is organized in two parts, an upper bank and a lower bank. The lower bank is directly addressed by a portion of the currently addressed control store word, whereas the upper bank is addressed by use of a multiplexer, with inputs thereto coupled from various logic elements. Apparatus is included to determine which part of the control store will be selected and to allow such determination at a time substantially after the addresses for the first and second parts have been received by the control store.

Abstract: A bit-oriented data link controller provides the interface between a microcomputer or terminal and a data communications link. The data link controller is capable of accommodating the three most commonly available bit-oriented data link control protocols, namely SDLC, HDLC, and ADCCP. The data link controller provides the data communications interface for both primary and secondary stations in stand-alone, polling, and loop configurations.

Abstract: Addressing control apparatus is structured to provide either byte or word addressing of storage organized on a word basis. The storage address register is made shiftable whereby for byte operations, it is shifted, and the bit shifted out of the register is used for byte selection. The contents of the storage address register are used to address storage for both word and byte addressing, and no change is required. The storage access, however, for byte addressing takes place after the shift is completed and the timing is adjusted to account for the shift operation. Gate control logic is modified to facilitate the byte selection.

Abstract: A system for analyzing asynchronous signals containing bits of information for ensuring the validity of said signals by sampling each bit of information a plurality of times and feeding the sampled pieces of bits of information into a sequence controller. The sequence controller has a plurality of maps or programs through which the sampled pieces of bits are stepped so as to identify the particular bit of information and determine the validity and phase of the bit. The step in which the sequence controller is clocked is controlled by a storage register. A data decoder decodes the information fed out of the storage register and feeds such information to shift registers for storage.