Abstract: To reduce the mean access time to storage blocks in CCD storage, a block which is most likely to be accessed next is detected after each access. While the accessed block is being processed, a selected block is moved at the high cyclic speed of the CCD storage to a shift position, and the CCD storage is then switched to the low speed. The distance of the shift position from a read/write position is such that it can be covered by the selected block at low speed within the mean time between two accesses to the CCD storage. At the time of the next access, the selected block is very likely to be close to the read/write position. In systems with virtual addressing, the block with the next virtual address would be the selected block. In other layouts, the access sequences to the CCD blocks are stored and are subsequently used to select the block which is most likely to be accessed next.

Abstract: An information processing system is used in a computer output microfilmer in which sub-information such as titles and indices is recorded on a recording medium such as a microfilm together with pre-processed main information obtained from a computer. The pre-processed main information is processed through a main information processing unit. The sub-information is prepared and processed through a sub-information processing unit in which key words contained in the main information are detected and the sub-information is prepared based on the key words. The output of the main information processing unit and the output of the sub-information processing unit are combined and recorded on the recording medium by means of a recorder.

Abstract: A data processing system embodying the present invention includes a plurality of data processing stations. Each station includes a first communications interface connected to a common communication channel and a second communications interface for communicating with one or more associated controlled units. Each station also includes a processor and a memory; the processor and the interfaces being operatively connected to the memory, so that each may access the memory, and to a contention resolving circuit for resolving memory access conflicts.

Abstract: A distributed data processing system including a general, passive, communications network, and a plurality of local systems which each have a central processing unit, associated memory, and at least one peripheral device. The control of the intercommunication is effected by respective system intercommunication processors, each interfacing one local system to the network. Each systems intercommunications processor is attached to the network by means of a respective communication module. A communication module has sequences for controlling in a first sequence of steps an addressed logical link from a source local system to a single destination local system and in a second sequence of steps controlling a broadcast logical link from a source local system to one or more destination local systems.

Abstract: In a buffer memory for a swap data block storage system, in the writing of data in an area of a size equal to or an integral multiple of a block of the buffer memory, when it is detected that a block including an address at which data to be written does not exist in the buffer memory, data is written in a replace block of the buffer memory directly without conducting at least an operation of moving out a block from a main memory.

Abstract: A peripheral processing controller controls access to a peripheral memory by specialized peripheral devices. The specialized peripheral devices process all of the data independently of a central processor that simply supervises the system. The controller uses Memory Address Registers (MARs) to control the access to the memory by the peripheral devices. Each peripheral device selects a MAR, and each MAR includes a mode register. The start address and mode are set in each MAR by the supervising central processor. Also, each peripheral device is set by the processor to select a MAR. When the controller grants each peripheral device access to the peripheral memory, the peripheral device uses whatever mode and starting address has been initialized for the MAR selected by the device. Each time the device accesses the memory, the address in the MAR is incremented so the MAR is ready for the next access. In this way, a peripheral device will advance through a block of memory space.

Abstract: A multiport memory architecture is disclosed for each of a plurality of task centers (11, 20, 30, 40) connected to a command and data bus (10). Each task center, (such as the center 11) includes a memory (13) and a plurality of devices (12, 14, 15, 17) which request direct memory access as needed. The memory (13) includes an internal data bus (53) and an internal address bus (50) to which the devices are connected, and direct timing and control logic (54) comprised of a 10-state ring counter (62) for allocating memory devices by enabling AND gates (64) connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates (66) to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence.

Abstract: A data processing system using microcode architecture in which a two-level microcode system comprises one or more first, or "horizontal", microinstructions and a plurality of second or "vertical", microinstruction portions in a vertical microcontrol store. In a preferred embodiment the vertical microinstruction portions include one or more "modifier" fields, a selection field for selecting a horizontal microinstruction and a sequencing field for selecting the next vertical microinstruction portion of a sequence thereof, one or more fields of the horizontal microinstructions being capable of modification by the vertical modifier fields in order to form output microinstructions for performing data processing operations.

Abstract: A digital device time-multiplexes the execution of multiple tasks that are defined by respective sequences of control words in a control memory. In this device, the time-multiplexing is performed by sending control signals that are representative of respective resume addresses along with each output message sent by the device that calls for a response. These response messages are thereafter received by the device along with the control signals that were sent with the corresponding output message. Received response messages are thereafter operated on by the device by executing control words in the control memory beginning at the resume address represented by the received control signals.

Abstract: In a data recovery system, encoded variable spaced digital data is recovered by provision of variable width windows which are expanded or narrowed so as to tend to center upon the expected occurrence of valid data based on knowledge of the contents of the current or the immediately preceding timing units and of characteristics of the encoding scheme. The system employs pulse-to-pulse synchronization without modifying the underlying synchronization of the system such that the first pulse of a two-pulse series serves as a window size reference for an immediately subsequent pulse. The window for a reference pulse is expanded at its trailing edge if, for example, the reference pulse is delayed beyond the tolerance of the detection system. The leading edge of a window for the subsequent pulse is expanded if no pulse occurs within a minimum period following the reference pulse.

Abstract: Process control apparatus for reading the condition of a selected variable and for generating a next instruction to be implemented based on the observed condition of the selected variable. The next instruction is that of reading one of two possible instructions, one of which causes the state of an output variable to be read and/or set and the other calls for reading the value of another selected input. In this manner, a program cycle is completed so that the values of all output variables can be set and read.

Abstract: An integrated circuit for operatively connecting a plurality of peripheral devices to a processor includes first, second, third and fourth sequentially located edges forming a rectangle. The integrated circuit includes two independent full duplex, master peripheral ports in which each port provides two character buffering on both input and output channels. Data may be transmitted using two message formats at two different clock frequencies with each channel having simultaneous sending and receiving capabilities. Data processing circuits are located adjacent the first edge which connects to the processor while the port control circuitry is located adjacent the third edge of the chip which connects to the peripheral devices.

Abstract: A word processing system is provided which includes a processing apparatus for processing textual information and for controlling a plurality of controlled units. The processing apparatus further includes a memory apparatus for storing such textual information. The system also includes a first controlled unit comprising a data entry device for entering textual and command information into the processing apparatus and a second controlled unit responsive to the processing apparatus for printing the textual information. The processing apparatus is responsive to the command information to perform editing operations, including insertion and deletion of characters on the textual information, to store in the memory apparatus the edited textual information and information defining the inserted and deleted characters and to select and print either the edited information, the information as originally stored in the memory apparatus or the edited information with the deletions restored.

Abstract: A variable field storage station having a control or access port and a periodic recirculating memory. A character set is employed which includes beginning delimiter and ending delimiter characters such that data in the form of structures and substructures therein can be nested to any level. One or more cursors are employed to specify storage locations between structures and substructures in which additional structures or substructures may be added. If data currently resides at that location it is read out and restored at new locations. When a structure or substructure is deleted, that space is allocated to other structures or substructures. In this manner, nested fields can be expanded or contracted as required.

Abstract: Apparatus is included in a main memory subsystem of a data processing system which receives multibyte data from a plurality of input/output devices connected to a common bus. During a write cycle of operation, a device applies the multibyte data signals together with associated parity bits for writing into an addressed storage location of memory. During the write cycle, error encoder circuits generate check code bits from the multibyte data and parity bits which are coded to signal selectively the presence of a multibyte uncorrectable error condition in accordance with the parity bits from a device. During a read cycle of operation, error detection and correction decoder circuits connected to the memory in response to the data and check bits read out from an addressed location are operative to generate a number of syndrome bits.

Abstract: A specialized peripheral-controller, designated as a data link processor, is used in an I/O subsystem to control data transfers from a main host computer into a peripheral train-printer mechanism. The peripheral-controller has a RAM buffer memory with a pluraity of addressable locations. Each addressable memory location stores two characters designated as the top character and the bottom character.

Abstract: A central processor through an asynchronous service processor, selectively resets an input/output channel designated in an instruction called Clear Channel that is executed by the central processor. As part of the execution of this instruction, the service processor also communicates a reset signal to the peripheral equipment associated with that channel in case the designated channel is malfunctioning and cannot relay a reset signal normally to the peripheral equipment associated with the designated channel. The reset signal for the peripheral equipment is supplied through a connection between the service processor and particular lines in I/O interface cables of that channel. Programming routines that use the Clear Channel instruction are designed to preserve the integrity of data held by peripheral equipment that is associted with two channels when the peripheral equipment has exclusive affiliations with the designated channel.

Abstract: A data processing system includes apparatus for addressing operands within a segment utilizing segment descriptors. The apparatus is responsive to instruction words executed by a first of a plurality of processes.

Abstract: A fully distributed computing system comprises several processors, each having an arbitrarily long unique logical address. A bidirectional bus connects each of the processors and is used for communicating information between and among processors, and for resolving requests from a competing set of processors desiring access to the bus for subsequent communication with another processor. Resolving apparatus, comprising pan-processor control lines and a resolution member within each processor, awards bus access to that competing processor having the lowest logical address. All control lines within the resolving apparatus are bidirectional; as a result, the system "fails soft," i.e., there is no single point of failure in the system; one of the processors can fail without disrupting the operation of the remainder of the system. Each processor's resolution member comprises one or more resolve elements, which can be single-bit, dual-bit, or multi-bit resolve elements.

Abstract: An alphanumeric search apparatus wherein a plurality of search indicia stored in a first operand and a plurality of elements stored in a second operand are operated upon by a data processing system to determine by means of search or verify operations whether any of the elements included in the second operand correspond to any one of the indicia included in the first operand. The second operand may be arranged in a sequential string of elements or in an array or table of elements and a search is conducted by comparing each element sequentially with all the search indicia and by so processing the elements until a match is found. A verify procedure is conducted by comparing each element with the search indicia to verify that there is a counterpart for each search element in the list of search indicia. For a search procedure, an output is generated indicating the storage locations within their respective operands of the search indicia and the element which produced the match.