Abstract: A data link processor, which is basically a peripheral-controller for interfacing a main host computer system to a peripheral terminal unit, forms part of an I/O subsystem in which a base module unit houses a plurality of such peripheral-controllers (data link processors). Each base module carries a distribution control circuit card which provides a communication interface between the main host computer and the peripheral-controller. A special line turn-around logic circuit is used to control the direction of data flow as between the distribution control circuit card and the data link processor. In one direction, data may flow from the distribution control circuit card (originating from the main host computer) into the data link processor. In the other direction, information and status data can flow from the data link processor to the distribution control circuit card (and then to the main host computer).

Abstract: For mutual bidirectional communication, two active functional units are connected by a bidirectional data bus line and one unidirectional control line for each of the two directions. Both active functional units are each time connected, via an output circuit, to the relevant single connections of the data bus line. The output circuits have at least one first state in order to produce per first state, at a low impedance, a first data state on the connection, and one second state for generating, at a high impedance, a second data state for the connection. When such a first and a second data states are simultaneously present on one and the same connection, the former state dominates. The second state can thus also act as an inactive state.

Abstract: A method for independently electronically collecting related market survey data from a plurality of diverse locations (6,6') for temporary storage at each of the independent diverse locations (6,6') where the data is collected for subsequent transmission thereof from these locations (6,6') over a telephone type link (30,36,42) for accumulative processing thereof at a remote central electronic data processor. An interactive interchangeable prompt message display is displayed on a visual display device (32) indicating one of a plurality of market survey categories in a predefined sequence. An actual data input signal may be provided via a keyboard (70) or barboard (29) and/or wand (18,28) in response to the prompt message display with this input being stored in a memory (16) for subsequent transmission. Prior to storage in the memory (16), the data is stored in a buffer and is displayed on the display device (32) to enable confirmation prior to transfer to the bulk memory (16).

Abstract: A system for reducing the computation required to match a misspelled word against various candidates from a dictionary to find one or more words that represent the best match to the misspelled word. The major facility offered is the ability to computationally discern the degree of apparent match that exists between words that do not perfectly match a given target word without requiring the computationally tedious procedure of character by character positional matching which necessitates shifting and realignment to accommodate for differences between the candidate and target words due to character differences or added and dropped syllables.

Abstract: In numerical controls of machine tools, the downwards (lengthwise) sum of the programmed information of each system program memory (SP1) is stored in an additional memory. For later checking of the memory contents, the downwards sums of the respective memories on the control side are formed and are compared with the stored information. If a sum deviates, a trouble signal is given out as an indication of the defective memory.

Abstract: An automated artwork generation system employs a video display and a microprocessor for verifying and editing data derived from a digitizer and utilized by a photoplotter. The system includes a data storage and retrieval apparatus in which data processed through the system is stored. The apparatus permits random access to data in a memory, and both the storing and retrieval times are minimized by establishing a direct relationship between the zone of a workpiece in which data is located and the portion of the memory in which the data is stored. Data entries in the memory are made in both a data entry file and a bulk data file. The entry file serves as an index to the bulk data file and contains abbreviated data entries and pointers identifying addresses in the bulk data file where additional related data is stored.

Abstract: In a data processing system, a central processor unit requests procedural data words or non-procedural data words stored in the system memory. A control store device executes firmware instructions including a local bus field for controlling the transfer of the requested procedural data words and non-procedural data words to the central processor unit.

Abstract: A time of day clock for a computer is run off a clock for the computer processor by selecting the processor clock cycle T such that a binary multiple N of the time of day unit cycle D contains an integral number K of processor cycles T or ND=KT in accordance with the equation:D=(R.+-.X/N)T,where R is the integer nearest the actual D/T ratio, while X represents the number of D cycles of longer or shorter duration than R processor cycles needed to establish the actual proportional relationship between the two cycles over the period ND.

Abstract: A first bank or a second bank of storage locations of a control store of a data processing system is enabled in response to one of a plurality of test signals received as parallel inputs by two multiplexer devices. Only one of the multiplexers is enabled at a given time in response to the polarity of one of the test signals selected from the inputs of the multiplexer devices.

Abstract: A data processing system includes a first memory for storing microinstructions in a first plurality of storage locations and second memory for storing microinstructions in a second plurality of storage locations. A central processor executing a series of addressed microinstructions to control the functions performed by this system generates the address of the next microinstruction to be executed in series as well as a next address selection signal. Addressing circuitry concurrently applies the next address generated by the processor to address inputs of each of the first memory and the second memory. After a predetermined delay, either the first memory or the second memory is selected to output an address microinstruction responsive to the value of the next address selection signal.

Abstract: A microprogram-controlled data processor executes a user instruction having an operation code field to specify the type of user instruction and at least one operand field to designate one of the general registers provided in a register file. The data processor comprises a logic circuit including the register file and at least one register connected directly to the register file for storing address data for addressing the register file. The data in the operand field of the user instruction is stored in the register during a microstep immediately before the first microstep of the microprogram for executing the user instruction. The output signal of the register designates one of the general registers provided in the register file.

Abstract: An input setting method for a protective relaying apparatus including an input setting switch for setting data, a digital operational device for carrying out a relaying operation utilizing the data, and a memory device for storing the data, the method comprising the steps of setting the data by the input setting switch, storing the data thus set in the memory device, comparing the set data with the stored data, carrying out the relaying operation utilizing the data when the compared data are found equal, and issuing an alarm signal when the compared data are found to be unequal.

Abstract: A bit-oriented data link controller provides the interface between a microcomputer or terminal and a data communications link. The data link controller is capable of accommodating the three most commonly available bit-oriented data link control protocols, namely SDLC, HDLC, and ADCCP. The data link controller provides the data communications interface for both primary and secondary stations in stand-alone, polling, and loop configurations.

Abstract: A semi-automatic picking system having pick modules associated with individual compartments of storage bays includes a switch, for manually decrementing or incrementing the module to indicate the number picked. One or more orders may be picked at the same time. Such information is stored for use with a data input device and a control unit.

Abstract: A microcomputer having a 4-bit instruction register uses some double operation code (opcode) instructions thereby increasing its instruction set over the sixteen instruction limit imposed by the instruction register. During a single opcode instruction operation, a 4-bit opcode word is fetched from memory (20), is loaded into the instruction register (32), and is applied to a logic circuit (601, 603 or 621, 623). The resulting output from the logic circuit (601, 603 or 621, 623) determines the state of a latching device (610 or 630). The latching device (610 or 630) is latched into a first state in response to the output of the logic circuit, and the first opcode word stored in the instruction register controls processing of a data word to be fetched from storage. During a double opcode instruction operation, a first opcode word is fetched into the instruction register. The latching device (610 or 630) is latched into a second state in response to the output of the logic circuit.

Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, data storage array, a decimal arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc., and to accommodate these different uses the output decoder is mask-programmable. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.

Abstract: A microinstruction processing unit of the type in which microinstructions are fed and executed in a predetermined sequence to process data in a data processing system in which, upon the feeding of a higher priority microinstruction, the execution of a lower priority microinstruction is interrupted but is subsequently carried out. Microinstructions lower than the highest priority rank are supplied to control the transfer of data to and from a storage register and to and from a priority rank designated position in a register file. Upon the interruption by has higher priority ranking microinstruction, the data for an interrupted microinstruction remains in the register file but it is replaced in the storage register by data the higher priority ranking microinstruction.

Abstract: A data capture circuit for a logic state analyzer includes a qualifier pattern comparator circuit that responds to a collection of input qualifier signals by producing a number of qualifier pattern signals each representative of the occurrence of a preselectable pattern in the input qualified signals. A like number of clock detection circuits each responds separately to the values of separate clock signals by producing separate qualified clock signals, each of the like number of which represents the simultaneous occurrence of a preselected transition in each particular clock signal and of a qualifier pattern signal associated with that clock signal. The several separate qualified clock signals generally occur at separate times, and each is used to individually capture into several temporary storage registers separate collections of data signal values occurring at those separate times.

Abstract: A data processor having a microprogrammed control store and including a conditional branch control unit for receiving selection bits output by the control store, selection bits from an instruction register, and conditional signals for generating a two-bit result which, when added to a base address, can specify one of two, three, or four branch destinations in the control store. The selection bits output by the control store determine whether the combination of conditional signals upon which the branch is dependent is selected by the control store or is selected directly by a bit field in the macroinstruction. Also, one of the selection bits output by the control store is used to select one of two possible output codes for the two-bit result associated with a particular branch destination.

Abstract: In a microcode control memory for a computer central processing unit, a network is provided for generating a modified microcode address in a sequence of instructions where the modified address is determined by a function of the results of preselected events.