Abstract: An information transferring apparatus comprises a central processing unit, and an input/output unit, a first-in first-out stack having a plurality of memory elements connected in series and being disposed between the central processing unit and the input/output unit, a command register which is set to a predetermined state under program control by the central processing unit, and a control circuit which receives a signal produced from the command register when the command register is set to a predetermined state and applies a signal designating the memory element which is to be the first memory element of the first-in first-out stack from which information is to be transferred and permits the information stored in the first memory element to be read out directly to the input/output unit.

Abstract: A programmable calculator having modular read-write and read-only memory units, a central processing unit, a keyboard input unit, and an output display unit, includes keys on the keyboard input unit for performing angular measurement unit conversion.

Abstract: A computer system comprising a plurality of channels, at least one main storage unit, and a memory control unit having a channel buffer between the main storage unit and the channels. The channel buffer comprises a memory portion divided into a plurality of tag blocks, tag lines, and a data memory portion having a plurality of data lines each corresponding to one of the tag lines. Two tag lines forming a set and each set of the tag memory portion is assigned to one of the channels.

Abstract: An asynchronous interface enables the transfer of information between a set of devices operating in a loop and having a wide range of operating speeds. Each device can enter a Controller active state in which it sources command frames to control the loop operation. Each device can also enter a Talker active state in which it sources Data frames on a Listener active state in which it received Data frames. The transfer of frames is coordinated by a set of handshakes which enable the frames to be transferred in an asynchronous manner.

Abstract: A dual mode microprocessor acts either as a front-end IO controller processor relative to a primary host processor and device or as a secondary data processor having independent storage, processing and IO capabilities. Host software prepares a list of device control block (DCB) arrays, which contain primary commands interpretable by the microprocessor so as to evoke these modes. Each DCB contains a chaining bit permitting its interpretation sequence to be chained (or not chained) to another DCB sequence, and a mode bit defining either a high speed DI/DO (HS) mode of operation or a programmable offline (PO) mode. In HS mode the microprocessor conditions associated adapters to transfer a specified amount of data between the host memory and device, performing this transfer in an autonomous manner, i.e., without assistance from either processor.

Abstract: A raster type display apparatus includes interlaced even-and-odd frames. A digital memory of a computer stores line segment data in locations which are sequentially read out to form a line segment display with overlapping line segments. The first line of one field is defined by a "O" start location and a third removed location for the end. The second line is defined by the fourth and seventh locations, and so forth. The first line of the second field starts with the last data taken plus two to access and define the line by the second and fifth locations, and so forth. The first field again reads the start to third locations, fourth to seventh, etc. Data points equal to twice the scan lines are displayed with each scan line spread over four data points. An off-scale detector prevents a line segment directly between the data points and creates a pair of line segments at the top and bottom of the display screen. An extended line from a break point in a curve to screen bottom is also prevented.

Abstract: An emulator control sequencer comprises a programmable state machine which passively monitors the data bus of an emulator microprocessor, extracts certain information indicative of internal processor behavior, such as when the next opcode fetch will occur, as well as detecting current opcodes, and generates control signals for the emulator.

Abstract: A multiprocessor system intercouples processors with an active logic network having a plurality of priority determining nodes. Messages are applied concurrently to the network in groups from the processors and are sorted, using the data content of the messages to determine priority, to select a single or common priority message which is distributed to all the processors with a predetermined total network delay time. Losing messages are again retried concurrently in groups at a later time. Message routing is determined by local acceptance or rejection of messages at the processors, based upon destination data in the messages. All messages occupy places in a coherent priority scheme and are transferred in contending groups with prioritization on the network.

Abstract: A meeting cost calculator and timer is shown for displaying the total cost of a meeting and the elapsed time thereof. Input switches, each associated with a class of attendee, actuate an adjustable rate indicator which applies its digital signal to an arithmetic logic unit and then to an accumulator in the form of a memory register. A second set of switches add or subtract the rate applied to the accumulator depending whether the attendee is entering or leaving the meeting. A display displays the total rate of the attendees over a period of time as the total cost of the meeting.

Abstract: A logic state analyzer monitors the ongoing succession of states occurring in a collection of digital signals, and stores in a memory either all such states or a selected subset thereof meeting certain qualification criteria. The oldest stored states are overwritten as the newest states are stored. Upon recognition of some trigger condition the logic state analyzer will subsequently store a preselected number of additional states, the collectivity of which may be termed the captured trace. The utility of such a trace in a logic state analyzer is enhanced by equipping the analyzer with a counting mechanism selectively responsive to a high speed clock signal or a programmable state detector. In the former case the counter operates as a timer whose value may represent either the elapsed time between consecutive states in the trace or between each state in the trace and an origin along a time axis.

Abstract: Operator keystrokes are processed in a text processor system to move a cursor on a display screen in either a vertical or horizontal direction or both without limitation as to the location of text. Keystroke data is processed under the control of programs stored in a random access memory. For a cursor motion, the random access memory of the system is structured to include a text storage buffer and a display control block both interconnected to an applications program and a display access method program. Data is stored in the text storage buffer in an unformatted configuration and the programs equate a contextual cursor address with a spatial cursor position. After running the display access method program in accordance with application program commands, a refresh buffer provides display signals to visually present by means of the display screen a cursor at an identified position in text.

Abstract: An interface circuit for a subsystem-controller is used in a data communications network. The interface circuit has a first (DLI) data link interface logic unit which includes a PROM sequencer which, when initiated by a master processor in the subsystem, acts to transfer data between a main host computer and a shared memory unit in the subsystem-controller. The interface circuit further includes a second (MLI) message level interface logic unit which is controlled by a slave processor (NDL) through the master (MLI) processor and functions to edit, translate and manage protocols for data transferred to and from a selected line communications processor which services a plurality of remote terminals.

Abstract: A memory system includes a high-speed, multi-region instruction cache, each region of which stores a variable number of instructions received from a main data memory said instructions forming part of a program. An instruction is transferred to a region from the main data memory in response to a program address and may be executed without waiting for simultaneous transfer of a large block or number of instructions. Meanwhile, instructions at consecutively subsequent addresses in the main data memory are transferred to the same region for building an expanding cache of rapidly accessible instructions. The expansion of a given region is brought about as a result of the addressing of that region, such that a cache region receiving a main line of the aforementioned program will be expanded in preference to a region receiving an occasionally used sub-routine.

Abstract: A copying machine has a microcomputer which is capable of actuating a plurality of processing components, including an automatic document feeder, a semi-automatic document feeder and a sorter, to continuously perform automatic copying with time sequence. This microcomputer has a random access memory. In the random access memory (RAM) are stored a series of programs for continuous copying specified at a keyboard by a user, that is, copying conditions such as a copying sheet number, modes of enlarged copying, reduced copying and copying of equal size, selection of an outfeed position of the sorter, selection of the automatic document feeder or the semi-automatic document feeder, and changes in paper sizes. The microcomputer controls respective components of the copying machine so as to perform continuous copying in response to the program stored in the RAM.

Abstract: An adaptable programmable calculator employs modular read-write and read-only memories separately expandable to provide additional program and data storage functions within the calculator oriented toward the environment of the user, and an LSI NMOS central processing unit, which includes the capability of bidirectionally transferring information between itself and various input/output units. The input/output units include a keyboard input unit having a full complement of alphanumeric keys, a magnetic tape cassette reading and recording unit capable of bidirectionally transferring programs and data between the calculator and a magnetic tape, a 32-character solid state output display unit capable of displaying every alphabetic and numeric character.

Abstract: A method of allocating memory space on a cyclic memory system is described. The memory system is partitioned into a plurality of memory regions with each of the regions containing contiguous memory elements. Each of the memory regions is then partitioned into a plurality of memory subregions wherein all subregions within a region are of equal memory capacity but where subregions of different regions have different memory capacities. A file of data is then assigned to occupy one available subregion of the memory which is the smallest available subregion which has sufficient memory capacity to contain the file of data.

Abstract: In a memory protection system for a computer, memory protection information provided for each of the memory areas of a memory and memory protection information provided for each of the programs executed by a processor are collated to determine allowance/inhibition of access to the memory. By detecting that an instruction to be executed is an instruction having a particular operation and that an address of the memory to be accessed by the instruction is a particular address, the memory protection information for the program executed by the processor is alterd to allow the memory access. The alteration of memory protection information is carried out with no intervention of a control program.

Abstract: System and apparatus for treating data derived in serial pulse fashion from a source such as a meter. Data words are recorded upon a magnetic bubble memory which is portable and which includes real time and identification data in addition to pulse source data. The portable storage device incorporating the magnetic bubble memory is inserted into reader apparatus for transmission by telecommunication to a translator station which may be located remotely from the reader station. Cyclical redundancy check verification of the transmission is made between the stations to assure proper transmission. Further, the translation station carries out data verification checks. Erase apparatus is provided in the vicinity of the reader apparatus to carry out a memory check for the magnetic bubble memory and an erasure thereof through the insertion of zeroes therewithin.

Abstract: A time accounting system for accounting for the time a process spends in a ready state, a wait state, or a running state. The system includes a time-of-day clock coupled to a central processing unit for outputting the time-of-day whenever a process changes state. A memory also coupled to the central processing unit stores the contents of a plurality of addressable process control blocks and each process control block includes first, second, and third storage locations for storing indications of the amount of time an associated process has been in the running, ready, and wait states, respectively. The central processor unit accesses the process control blocks and updates the process times stored therein in accordance with control signals generated by decoding a string of microinstructions stored in a control store memory. The time-of-day clock is accessed each time a process enters one of the running, ready, or wait states and each time the execution of a process is completed.

Abstract: Permits one program in one address space to obtain access to data in another address space without invoking a supervisor. Each of a plurality of address spaces assigned an Address Space Number (ASN) has an associated set of address translation tables. Addressability to a second address space may be specified by a program if authorized in accordance with the entry of an authority table associated with the second address space, the entry being designated by an authorization index associated with the program.