Patents Examined by Hashem Farrokh
  • Patent number: 10956059
    Abstract: Methods, apparatus, and processor-readable storage media for classification of storage systems and users thereof using machine learning techniques are provided herein. An example computer-implemented method includes processing input data pertaining to multiple storage systems within an enterprise; classifying one or more of the storage systems by applying a first set of machine learning techniques to the processed input data; classifying one or more respective users of the classified storage systems by applying a second set of machine learning techniques to the processed input data associated with the classified storage systems; and outputting, via one or more user interfaces, at least a portion of the storage system classifications and at least a portion of the user classifications to a user for use in connection with storage system configuration actions and/or an entity within the enterprise for use in connection with user-support actions.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 23, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Bina K. Thakkar, Roopa A. Luktuke, Aditya Krishnan, Chao Su, Deepak Gowda
  • Patent number: 10949355
    Abstract: Aspects of the present disclosure provide various apparatus, devices, systems and methods for dynamically configuring a cache partition in a solid state drive (SSD). The SSD may include non-volatile memory (NVM) that can be configured to store a different number of bits per cell. The NVM is partitioned into a cache partition and a storage partition, and the respective sizes of the partitions is dynamically changed based on a locality of data (LOD) of the access pattern of the NVM.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: March 16, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Avichay Haim Hodes, Oren Cohen, Judah Gamliel Hahn
  • Patent number: 10949345
    Abstract: Enhanced data buffer control in data systems is presented herein. In one example, a method includes establishing a pool of available memory pages tracked by memory pointers for use in a data structure, and processing requests for storing data to identify ones of the requests indicating data sizes that exceed a capacity of current pages included in the data structure. The method includes providing first pointers indicating start locations in the data structure to begin writing associated data, count information indicating quantities of the associated data able to be written in the current pages, and second pointers indicating at least one additional page in the data structure into which the associated data can be spanned from the current pages, where the at least one additional page is allocated from the pool of available memory pages in accordance with a fullness threshold for the data structure.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: March 16, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jason Matthew Gould, Ivan Nevraev
  • Patent number: 10948972
    Abstract: The present invention discloses a data storage apparatus and an operation method thereof. The data storage apparatus includes a non-volatile memory, a volatile memory coupled to the non-volatile memory, and a memory controller coupled to the non-volatile memory and the volatile memory. The memory controller is configured to perform following operations: receiving a modern standby notification from a host; and updating a second mapping table stored in the non-volatile memory according to a number of flags and a first mapping table stored in the volatile memory.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: March 16, 2021
    Assignee: ACER INCORPORATED
    Inventors: Yi-Jhong Huang, Tz-Yu Fu
  • Patent number: 10949094
    Abstract: A storage device includes a data buffer, a device controller, and nonvolatile memories. The data buffer is configured to transact data from an external device. The device controller is configured to receive a command and an address from an external device, to control the data buffers, and to transact data with the data buffers. The nonvolatile memories are configured to perform write, read, and erase operations under control of the device controller. When a first link training between an external device and the data buffers is performed by the external device, the device controller performs a second link training between the device controller and a data buffer internally without control of the external device.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Ju Lee, Youngkwang Yoo, Youngjin Cho
  • Patent number: 10936191
    Abstract: An exemplary access control system controls access to a computing system such as a data storage system. For example, the exemplary access control system includes a remote management system that receives a request to operate on an element of the computing system and generates a message based on the request and a first token for the remote management system that is associated with the request. The message includes data representative of a second token for the remote management system. The remote management system signs the message and transmits the signed message to the computing system, which is configured to verify and use the signed message, including the second token included in the signed message, to obtain and use a local access token to access and operate on the element in accordance with the request.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: March 2, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Sitaraman Suthamali Lakshminarayanan, Christopher Holtz, Jonathan McLachlan, Li Zhao, David M'Raihi, Yu Tan
  • Patent number: 10936484
    Abstract: A memory system includes: a memory device including super memory blocks each having a plurality of memory blocks; a garbage collection operation time manager suitable for determining an operation time of a garbage collection operation according to a number of valid pages, distribution of the valid pages and distribution of logical addresses of the valid pages; and a garbage collection operation module suitable for controlling the memory device to perform the garbage collection operation within the determined operation time.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 2, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 10929035
    Abstract: Disclosed herein are system, method, and computer program product (computer-readable storage medium) embodiments for implementing memory management via dynamic tiering pools. An embodiment operates by initializing a first memory pool of a first tier, and invoking first and second function calls to allocate memory to the first memory pool. Responsive to these function calls, an OS may allocate differently-sized memory elements for attachment to the first memory pool, from a memory free store managed by the OS. A second memory pool, of a second tier, may be further initialized, and a third function call may be invoked, to allocate memory to the second memory pool. Here, in response to the third function call, the first memory pool may reallocate the second memory element from the first memory pool for attachment to the second memory pool.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: February 23, 2021
    Assignee: SAP SE
    Inventors: Xia-Ge Dai, Guo Gang Ye, Shao-Yi Ning, Guangquing Zhong
  • Patent number: 10929296
    Abstract: This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional program instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetches the lower half level two cache line employing fewer resources than an ordinary prefetch.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: February 23, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Oluleye Olorode, Ramakrishnan Venkatasubramanian, Hung Ong
  • Patent number: 10922017
    Abstract: Memories, and systems incorporating similar memories, as well as their operation, where the memory might include an array of memory cells, a status register, and a controller configured to access the array of memory cells. The controller may further be configured to perform a plurality of read operations on the array of memory cells in response to a read command associated with a plurality of addresses, store a particular value to the status register in response to data of a particular read operation corresponding to a particular address of the plurality of addresses being available for readout by an external device, and store a different value to the status register in response to data of a different read operation corresponding to a different address of the plurality of addresses being available for readout by the external device.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Vipul Patel, Theodore T. Pekny
  • Patent number: 10901906
    Abstract: This disclosure provides a method, a computing system and a computer program product for allocating write data in a storage system. The storage system comprises a Non-Volatile Write Cache (NVWC) and a backend storage subsystem, and the write data comprises first data whose addresses are not in the NVWC. The method includes checking fullness of the NVWC, and determining at least one of a write-back mechanism or a write-through mechanism as a write mode for the first data based on the checked fullness.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Gang Lyu, Hui Zhang
  • Patent number: 10896129
    Abstract: A system and method for providing storage virtualization (SV) is disclosed. According to one embodiment, a system includes a storage device having a tier 1 cache and a Tier 2 storage, an operating system and a file system having a Tier 0 memory cache that stores application data. The Tier 0 memory cache synchronizes the application data with the tier 1 cache and the Tier 2 storage.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: January 19, 2021
    Assignee: Dynavisor, Inc.
    Inventor: Sreekumar Nair
  • Patent number: 10891055
    Abstract: Data address management systems, methods, devices and uses for minimizing interaction with data consumers' data on data storage devices, an embodiment comprising an external bus for communicatively interfacing the data storage system and data consumers; at least one storage medium components, each storage medium component comprising a plurality of storage locations having a unique storage location indicators; a translation layer module comprising a data address space having data addresses associable with storage location indicators; and a controller configured to store data in the storage locations and creating associations in the translation layer module between data addresses and the physical location indicators; wherein the data address space is accessible by the data consumer for addressing requests relating to data stored on the storage device and wherein the controller is configured to manipulate the arrangement of the data addresses in the data address space.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: January 12, 2021
    Assignee: OPEN INVENTION NETWORK LLC
    Inventors: Andrew Warfield, Timothy John Deegan, Keir Fraser, Daniel Stodden, Kevin Jamieson
  • Patent number: 10891164
    Abstract: Provided is to appropriately allocate resources among the versions in the system, the resource setting control device includes: determination unit that extracts a load pattern of a service request in a specific period of time from a) a request history, including information of a group, the requested version, and a resource usage during execution of the service, and b) the request history in operation information storage, and updates the reference pattern when detecting that change from the reference pattern is beyond a specific range; and change unit that determines, for each of the versions, a resource request amount, based on a peak value of the resource usage in the specific period of time and a number of server devices providing the version, when detecting the load pattern change, and outputs the determined resource request amount.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: January 12, 2021
    Assignee: NEC CORPORATION
    Inventor: Takumi Fujiwara
  • Patent number: 10884665
    Abstract: A data reading method is provided. The method includes using X read voltage sets to read a target word line, so as to obtain X read results; in a first order, updating a final Gray code index of each of a plurality of target memory cells of the target word line, and obtaining (X?1) abnormal Gray code count sets according to the X read results, wherein an ith read result among the X read results includes a Gray code corresponding to an ith read voltage set of each of the target memory cells, and the Gray code corresponds to one of N Gray code indexes; and selecting (N?1) optimized read voltages from (X?1)*(N?1) read voltages of the corresponding (X?1) read voltage sets to form an optimized read voltage set according to the obtained (X?1) abnormal Gray code count sets.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: January 5, 2021
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventors: Yu-Hua Hsiao, Chia-Wei Chang
  • Patent number: 10884742
    Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto, Albert J. Van Norstrand, Jr.
  • Patent number: 10871916
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may control a memory device in response to a command received from a host. The memory controller may include a write amplification factor (WAF) storage and a standby state controller. The WAF storage may store a WAF of the memory device. The standby state controller may control entry of the memory controller into a standby state based on a value of the WAF stored in the WAF storage.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: December 22, 2020
    Assignee: SK hynix Inc.
    Inventor: Young Kyun Shin
  • Patent number: 10872037
    Abstract: Systems and methods for estimating the number of workers needed to perform a garbage collection operation are disclosed. Similarity groups are used to identify segments associated with objects in a computing system. Using deletion records that identify objects to be deleted, the similarity groups impacted by the deletion records can be identified. The number of workers can be determined based on the impacted similarity groups. More specifically, the number of impacted similarity groups and/or workers can be evaluated in terms of memory requirements, input/output constraints and/or time requirements to estimate the number or workers needed to clean similarity groups impacted by a garbage collection operation.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: December 22, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Nicholas A. Noto, Mariah Arevalo, Philip Shilane, Joseph S. Brandt
  • Patent number: 10861551
    Abstract: A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so that current flows through the first and second memory cells, and generating an output responsive to the current. The first voltage and a threshold voltage of the second memory cell can be such that the current is proportional to a product of the first voltage and the threshold voltage of the second memory cell.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Minucci, Tommaso Vali, Fernanda Irrera, Luca De Santis
  • Patent number: 10845991
    Abstract: The technology describes shallow memory tables, comprising data maintained at a backup node of a data storage system that contain digest information related to a main node memory table that represents a metadata tree. If the main node fails, the shallow memory table's digest information contains sufficient information to recover the failed main node's memory table data. In response to receiving an update operation at a main node, the main node updates a memory table, journals an update record in a tree-related journal, and sends a digest representing the update to a backup node, which maintains the digest in a shallow memory table. If the main node fails, the backup node transforms the shallow memory table into a memory table by using the digest information to locate the corresponding update journal records. The backup node is able to handle create, read, update and delete requests during the transformation.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: November 24, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Konstantin Buinov