Abstract: A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so that current flows through the first and second memory cells, and generating an output responsive to the current. The first voltage and a threshold voltage of the second memory cell can be such that the current is proportional to a product of the first voltage and the threshold voltage of the second memory cell.

Abstract: The technology describes shallow memory tables, comprising data maintained at a backup node of a data storage system that contain digest information related to a main node memory table that represents a metadata tree. If the main node fails, the shallow memory table's digest information contains sufficient information to recover the failed main node's memory table data. In response to receiving an update operation at a main node, the main node updates a memory table, journals an update record in a tree-related journal, and sends a digest representing the update to a backup node, which maintains the digest in a shallow memory table. If the main node fails, the backup node transforms the shallow memory table into a memory table by using the digest information to locate the corresponding update journal records. The backup node is able to handle create, read, update and delete requests during the transformation.

Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.

Abstract: In one embodiment, a system for managing a virtualization environment comprises a plurality of host machines, one or more virtual disks comprising a plurality of storage devices, a virtualized file server (VFS) comprising a plurality of file server virtual machines (FSVMs), wherein each of the FSVMs is running on one of the host machines and conducts I/O transactions with the one or more virtual disks, and a virtualized file server backup system configured to back up data stored in a VFS located a cluster of host machines to an object store, and retrieve the backed-up data as needed to restore the data in the VFS. The object store may be located in a public cloud. The object store may include a low-cost storage medium within the cluster. An FSVM of the VFS may provide an object store interface to low-cost storage media.

Abstract: According to one embodiment, a memory system includes a memory and a controller electrically connected to the memory. The memory includes blocks. Each of the blocks includes one or more sub-blocks. Each of the one or more sub-blocks includes nonvolatile memory cells. The controller is configured to obtain read frequency of at least one of the sub-blocks, and move data stored in the at least one of the sub-blocks so that data having substantially the same read frequency are written into one block.

Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.

Abstract: A cache is disclosed in which a dedicated cache portion comprising one or more extra lines dedicated for data of a particular data type is provided alongside a shared cache portion. So long as there is a cache line available in the shared cache portion, data can be written into the shared cache portion. However, when the shared cache portion is fully locked such that no new data can be written into the shared cache portion, data can instead be written to its respective dedicated cache portion, effectively bypassing the fully locked shared cache portion.

Abstract: A computer device, a server device, and a method for controlling a hybrid memory unit thereof are provided. The control method includes: executing, by a processing unit, an operating system (OS) in a working mode of the computer device; triggering, by a soft off control signal or a soft reset control signal when the processing unit executes the OS, the processing unit to enter an interrupt processing mode; executing, by the processing unit, basic input/output system (BIOS) program code in the interrupt processing mode; and controlling, by the processing unit by using the BIOS program code, to store data from a volatile memory into a non-volatile memory corresponding to the volatile memory.

Abstract: A data storage device is presented that includes a plurality of storage drives each comprising an associated drive Peripheral Component Interconnect Express (PCIe) interface. The data storage device also includes a control system configured to receive, over a host PCIe link, write operations for storage of data by the data storage device. The control system is configured to process the write operations against storage allocation information to apportion the data for storage among more than one of the storage drives, and transfer corresponding portions of the data to associated storage drives over corresponding drive PCIe interfaces.

Abstract: A convergence memory device includes a plurality of memories and a controller configured to control the plurality of memories. When an access request for accessing a storage region included in one or more of the memories is received, the controller determines whether the access request has been received a preset number of times or more within a refresh cycle. When the controller determines that the access request has been received the preset number of times or more, the controller postpones processing of the received access request.

Abstract: A method of operating a storage device which includes a non-volatile memory including a normal unit configured to store normal data and a swap unit configured to store swap data and a controller configured to control the non-volatile memory is provided. The method includes receiving the swap data and a unit selection signal for selecting the swap unit from a host; and processing the swap data according to a data processing policy of the swap unit and writing the processed swap data to the swap unit. The data processing policy of the swap unit may be different from a data processing policy of the normal unit.

Abstract: A method controlling near caches in a distributed cache environment including distributed cache servers is provided. The method includes steps of: a specific distributed cache server among the distributed cache servers, if a request signal for original cache data is obtained from a client node, transmitting replicated cache data for the original cache data to the client node, to support the client node to store and refer to the replicated cache data in its corresponding near cache storage part, and managing a reference map with a correspondence between the client node referring to the replicated cache data, and the original cache data; and if the original cache data is changed, checking the number of the client nodes referring to the replicated cache data by referring to the reference map, and invalidating the replicated cache data according to the number of the checked client nodes.

Abstract: The data storage device including a buffer configured to receive first information including first data and a first stream class number identifying characteristics of the first data and second information including second data and a second stream class number identifying characteristics of the second data and store the first and second information therein, the second stream class number being different from the first stream class number, a non-volatile memory including a shared memory area and a dedicated memory area different from the shared memory area and configured to store the first and second data stored in the buffer, the non-volatile memory, and a controller configured to control the buffer and the non-volatile memory, the controller configured to store the first and second data stored in the shared memory area, and then migrate the first data stored in the shared memory area to the dedicated memory area may be provided.

Abstract: A security system for an external data storage apparatus and a control method thereof are disclosed. The system utilizes an input ID to selectively permit data to be written and/or read.

Abstract: Disclosed are some implementations of systems, apparatus, methods and computer program products for facilitating data migration. Data migration is customizable according to user-specified data formats. A data migration system monitors the data migration process and automatically retries data migration tasks that have failed. In addition, the results of data migration are reversed according to detected threshold conditions.

Abstract: A memory system includes: a memory device; a candidate logical block address (LBA) sensor suitable for detecting a start LBA of a sequential workload as a candidate LBA, and, when a ratio of the number of update blocks to a total sum of valid page decrease amounts is less than a first threshold value, caching the candidate LBA in a loop cache; and a garbage collector suitable for performing a garbage collection operation on a victim block, when the number of free blocks in the memory device is less than a second threshold value and greater than or equal to a third threshold value and a start LBA of a subsequent sequential workload is not the same as the cached candidate LBA.

Abstract: A method for operating a data storage device including memory regions each including memory units of levels, the levels respectively corresponding to bitmaps, and each of the bitmaps including entries respectively corresponding to the memory regions includes controlling a read operation for a first memory unit of a first level among the levels in a first memory region among the memory regions; increasing a read count by checking a first entry corresponding to the first memory region in a first bit map corresponding to the first level, wherein each of entries included in the first bitmap reflects whether a corresponding memory region is included in at least one second memory region in which a memory unit of the first level has been read, during a predetermined period before the read operation for the first memory unit; and performing a management operation for the memory regions, based on the read count.

Abstract: A system and method for early data pipeline lookup in large cache design is provided. An embodiment of the disclosure includes searching one or more tag entries of a tag array for a tag portion of the memory access request and simultaneously with searching the tag array, searching a data work queue of a data array by comparing a set identifier portion of the memory access request with one or more data work queue entries stored in the data work queue, generating a pending work indicator indicating whether at least one data work queue entry exists in the data work queue that corresponds to the set identifier portion, and sending the memory access request to the data array or storing the memory access request in a side buffer associated with the tag array based on the pending work indicator and a search result of the tag array search.

Abstract: An exemplary method to rank blocks of a non-volatile memory device includes: for each of a plurality of blocks of a memory device, determining a respective erase health metric (EHM) for each of the blocks by combining an erase difficulty metric and an age metric, including: calculating the erase difficulty metric for a respective block based on erase performance metrics obtained during erase phases of an erase operation performed on the respective block, and determining the age metric for the respective block based on a total number of erase operations performed on the respective block during its lifespan. After determining the respective EHM for each of the blocks, the method includes ranking blocks in accordance with the determined respective EHMs, and selecting a block of the plurality of blocks in accordance with the rankings, and writing data to the selected block.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.