Patents Examined by Henry Choe
  • Patent number: 11929539
    Abstract: A directional coupler is configured so as to include: a resistive element in which one end thereof is connected to a first terminal and the other end is connected to a second terminal; a first amplifier circuit for outputting either a current directly proportional to a first voltage applied to the one end of the resistive element or a current directly proportional to a second voltage applied to the other end of the resistive element; a second amplifier circuit for outputting a first current which is directly proportional to the voltage difference between the first voltage applied to the one end of the resistive element and the second voltage applied to the other end of the resistive element and whose polarity is different from that of the current outputted from the first amplifier circuit when a signal is flowing from the first terminal to the second terminal, and for outputting a second current which is directly proportional to the voltage difference between the first voltage and the second voltage and whose
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: March 12, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takanobu Fujiwara, Tatsuya Hagiwara, Masaomi Tsuru
  • Patent number: 11923808
    Abstract: Low noise amplifiers (LNAs) with low noise figure are provided. In certain embodiments, an LNA includes a single-ended LNA stage including an input for receiving a single-ended input signal from an antenna and an output for providing a single-ended amplified signal, a balun for converting the single-ended amplified signal to a differential signal, and a variable gain differential amplification stage for amplifying the differential signal from the balun. Implementing the LNA in this manner provides low noise figure, high gain, flexibility in controlling gain, and less sensitivity to ground/supply impedance.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: March 5, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: Sanjeev Jain, Haoran Yu, Nan Sen Lin, Gregory Edward Babcock, Kai Jiang, Hassan Sarbishaei
  • Patent number: 11923806
    Abstract: Envelope tracking power supply circuitry includes a look up table (LUT) configured to provide a target supply voltage based on a power envelope measurement. The target supply voltage is dynamically adjusted based on a delay between the power envelope of an RF signal and a provided envelope tracking supply voltage. The envelope tracking supply voltage is generated from the adjusted target supply voltage in order to synchronize the envelope tracking supply voltage with the power envelope of the RF signal.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: March 5, 2024
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 11923812
    Abstract: A delay-compensating power management integrated circuit (PMIC) is provided. The PMIC includes a target voltage circuit configured to generate a target voltage that is utilized for generating a time-variant voltage to amplify an analog signal. The target voltage is generated based on a time-variant envelope of the analog signal but lags behind the time-variant envelope by a temporal delay(s) due to an inherent processing delay in the target voltage circuit. In this regard, a voltage processing circuit is provided in the target voltage circuit to generate a modified target voltage that is time-adjusted relative to the target voltage to substantially offset the temporal delay(s). By generating the time-variant voltage based on the modified target voltage, the time-variant voltage can be better aligned with the time-variant envelope of the analog signal, thus helping to reduce amplitude distortion when amplifying the analog signal.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: March 5, 2024
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 11923815
    Abstract: An integrator having an offset evaluation circuit and a collected charge reduction circuitry and method for using the integrator. The integrator includes an amplifier, operable to amplify an input signal, an integration capacitor for collecting charge indicative of a level of the input signal and an offset capacitor. The offset evaluation circuit is operable to charge the offset capacitor with charge corresponding to an offset voltage of the amplifier and the collected charge reduction circuitry is operable to collect charge resulting from disconnection of the offset evaluation circuit, thereby reducing an amount of charge and associated noise input to the amplifier.
    Type: Grant
    Filed: June 5, 2022
    Date of Patent: March 5, 2024
    Assignee: TriEye Ltd.
    Inventors: Shimon Elkind, Nadav Melamud
  • Patent number: 11923811
    Abstract: A high-frequency power amplifier is configured in such a way as to include an input matching circuit, an amplifying element, an output matching circuit, a coupling circuit, a detection circuit, and an output terminal, and in such a way that either the input matching circuit or the output matching circuit has an active element, the detection circuit receives a signal outputted by the coupling circuit and outputs a control voltage into which the detection circuit converts the signal to the active element, and the active element changes the impedance of the active element in accordance with the control voltage outputted by the detection circuit, thereby changing the power of a signal outputted by either the input matching circuit having the active element or the output matching circuit having the active element, to change the power of a signal which the coupling circuit outputs to the output terminal.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: March 5, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Ryota Komaru, Masatake Hangai, Shintaro Shinjo
  • Patent number: 11923814
    Abstract: An amplifying circuit and a rectifying antenna are provided. The amplifying circuit includes: a first rectifying circuit (20), configured to output a first direct current signal according to an alternating current signal; a second rectifying circuit (30), configured to output a second direct current signal according to the alternating current signal; a differential amplifying circuit (40), configured to receive the first direct current signal and the second direct current signal, amplify a difference between the first direct current signal and the second direct current signal, and output an amplified difference between the first direction current signal and the second direct current, the first direct current signal and the second direct current signal have directions opposite to each other. The amplifying circuit can improve sensitivity of an antenna with relatively low costs.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: March 5, 2024
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tien Lun Ting, Xiangzhong Kong, Lei Wang, Ken Wen
  • Patent number: 11916520
    Abstract: A Doherty amplifier including a main amplifier and a peak amplifier is mounted on a package substrate. A low noise amplifier is further mounted on the package substrate. A transmit/receive switch switches in terms of time between a transmission connection state in which an output signal of the Doherty amplifier is supplied to an antenna and a reception connection state in which a signal received by the antenna is inputted to the low noise amplifier.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: February 27, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kiichiro Takenaka, Satoshi Arayashiki, Satoshi Sakurai
  • Patent number: 11916518
    Abstract: Examples provide methods and apparatus for controlling a DC bias current in an RF amplifier. In one example where the RF amplifier is implemented on an amplifier die, a reference voltage is produced across a reference resistor implemented on the amplifier die, the DC bias current is measured, and a current controller, which is implemented on a controller die that is separate from the amplifier die, operates a feedback loop using the reference voltage to control a level of the DC bias current.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: February 27, 2024
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Douglas M. Johnson, Guillaume Alexandre Blin, Michael John Mitzen, Jung Hee Lee, Weize Xu, Attila Kalamar
  • Patent number: 11909363
    Abstract: A radiofrequency power amplifier includes a balun transformer and a plurality of power transistor pairs arranged in a push-pull configuration. The balun transformer has an unbalanced coil extending between a first single-ended signal terminal and a first reference, and a balanced coil extending between a first balanced signal terminal and a second balanced signal terminal. The balun transformer also includes an auxiliary coil electrically isolated from the unbalanced coil and the balanced coil. The auxiliary coil is inductively coupled to the unbalanced coil and extends between a third balanced signal terminal and a fourth balanced signal terminal forming a balanced combiner-divider. An output of a first one of the power transistor pairs is coupled to the first and second balanced signal terminals and an output of a second one of the power transistor pairs is coupled to the third and fourth balanced signal terminals.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: February 20, 2024
    Assignee: PRODRIVE TECHNOLOGIES INNOVATION SERVICES B.V.
    Inventor: Bart Gerardus Maria Van Ark
  • Patent number: 11909357
    Abstract: An amplifier includes an amplification circuit, a power supplying circuit and an input circuit. A first end of the amplification circuit is connected with a first end of the input circuit; a second end of the amplification circuit is connected with the power supplying circuit; and a third end of the amplification circuit is connected with a second end of the input circuit. The power supplying circuit is at least configured to supply power to the amplification circuit so that the amplification circuit operates in an amplification region. The input circuit is at least configured to receive an input signal; the amplification circuit is configured to obtain an amplification gain in case of operating in the amplification region, and amplify the input signal by using the obtained amplification gain.
    Type: Grant
    Filed: December 25, 2020
    Date of Patent: February 20, 2024
    Assignee: SMARTER MICROELECTRONICS (GUANG ZHOU) CO., LTD.
    Inventors: Zhenfei Peng, Qiang Su
  • Patent number: 11909361
    Abstract: The invention discloses a broadband logarithmic detector with high dynamic range, comprising a low noise amplifier, a compensate detection unit, a current summation and driving unit, an N-stage clipper amplifier and an N-stage detection unit. The invention improves the detection sensibility of the overall detector by adding a low noise amplifier before the first-stage clipper amplifier and extends the dynamic detection range of the overall detector through combination of the low noise amplifier and the compensate detection unit.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: February 20, 2024
    Assignee: NANJING MILLIWAY MICROELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jianjun Wu, Mengjiao Si, Ying Zhang
  • Patent number: 11901288
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element, and a multilayer wiring. The semiconductor element is formed on the semiconductor substrate. The multilayer wiring includes a wiring electrically connected with the semiconductor element, and a first inductor. The multilayer wiring is formed on the semiconductor substrate such that the multilayer wiring covers the semiconductor element. The first inductor is formed such that the first inductor electrically isolated from the wiring and is magnetically connected with the wiring.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 13, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Iida, Yasutaka Nakashiba, Shinichi Uchida
  • Patent number: 11894815
    Abstract: A power amplifier includes: a power amplification circuit and a linearity compensation circuit; and herein the linearity compensation circuit is connected between a transistor amplification circuit and a biasing circuit of the power amplification circuit, to linearly compensate a nonlinear distortion of the power amplification circuit.
    Type: Grant
    Filed: December 26, 2020
    Date of Patent: February 6, 2024
    Assignee: SMARTER MICROELECTRONICS (GUANG ZHOU) CO., LTD.
    Inventors: Qiang Su, Ping Li
  • Patent number: 11894826
    Abstract: An apparatus includes a radio-frequency (RF) apparatus, and a multi-band matching balun coupled to the RF apparatus. The multi-band matching balun including a plurality of capacitors and a plurality of inductors. None of the plurality of capacitors and none of the plurality of inductors is variable or tunable.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: February 6, 2024
    Assignee: Silicon Laboratories Inc.
    Inventors: Zoltan Vida, Attila L. Zolomy
  • Patent number: 11888454
    Abstract: A blocking signal cancellation low noise amplifier system includes a first low noise amplifier, a second low noise amplifier, a blocking signal extraction and bias generation circuit, a bias switching circuit, and a bias switching signal generating circuit. The first low noise amplifier is used for dynamic input matching, and the first low noise amplifier receives an input signal and outputs it after amplifying. The blocking signal extraction and bias generation circuit is used to extract a blocking signal from the output signal of the first low noise amplifier, and output a DC voltage signal. The bias switching circuit is used to switch the first low noise amplifier between a blocking mode and a small signal mode. The bias switching signal generating circuit is used to compare the DC bias voltage signal VB2 with a preset reference voltage signal Vref.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: January 30, 2024
    Assignee: THE CHINESE UNIVERSITY OF HONG KONG, SHENZHEN
    Inventors: Liang Wu, Yifu Li, Xiaoping Wu, Shiyuan Zheng
  • Patent number: 11888452
    Abstract: Amplifier having input power protection. In some embodiments, an amplifier circuit can include an input node and an output node, and an amplifier implemented between the input node and the output node. The amplifier circuit can further include a bias circuit configured to provide a bias signal to the amplifier. The amplifier circuit can further include a protection circuit configured to generate a detected voltage representative of a peak of a radio-frequency signal present at the input node. The protection circuit can be further configured to enable a protection mode when the detected voltage is greater than a first threshold value and to disable the protection mode when the detected voltage is less than a second threshold value that is less than the first threshold value.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: January 30, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventor: Paul Raymond Andrys
  • Patent number: 11881823
    Abstract: A power amplifier circuit includes a power amplification circuit and a diode assembly. The diode assembly is connected in series with a transistor amplification circuit of the power amplification circuit, and the transistor amplification circuit is configured to, when load of power amplifier is mismatched, turn the diode assembly on, so as to divide current voltage to at least two electrodes of the transistor amplification circuit.
    Type: Grant
    Filed: December 27, 2020
    Date of Patent: January 23, 2024
    Assignee: SMARTER MICROELECTRONICS (GUANG ZHOU) CO., LTD.
    Inventors: Yongle Li, Limin Yu
  • Patent number: 11881820
    Abstract: A power control circuit includes a negative feedback loop, and a radio frequency signal path including a first NMOS transistor having a gate configured as a radio frequency signal input end, a drain connected with a source of a second NMOS transistor, and a source connected with a ground terminal. A drain of the second NMOS transistor is configured as a radio frequency signal output end and connected with a first voltage source. The negative feedback loop includes a third NMOS transistor having a gate connected with an output end of a differential amplifier, a source connected with the ground terminal, and a drain connected with a source of a fourth NMOS transistor having a gate connected with a reverse input end of the differential amplifier and with a second voltage source, and a drain connected with a forward input end and a first bias current source.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: January 23, 2024
    Assignee: SMARTER MICROELECTRONICS (GUANG ZHOU) CO., LTD.
    Inventors: Chifeng Liu, Qiang Su, Qiming Wang, Jiangtao Yi
  • Patent number: 11876489
    Abstract: Provided is a dual-drive based Doherty amplifier that includes a first power amplifier and a second power amplifier that is in parallel with the first power amplifier. The first power amplifier is configured to receive a first portion of a signal having a first phase, and the second power amplifier is configured to receive a second portion of the signal having a second phase that has a phase difference from the first phase. At least one of the first power amplifier or the second power amplifier includes a dual-drive power amplifier core.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: January 16, 2024
    Assignee: Falcomm, Inc.
    Inventors: Edgar Garay, Sanghoon Lee