Patents Examined by Henry Choe
  • Patent number: 12732140
    Abstract: This disclosure is directed to a power amplifier including a programmable impedance matching circuit. The programmable impedance matching circuit may include a programmable primary inductor and a secondary inductor. The programmable primary inductor may adjust a center frequency (e.g., resonant frequency) for providing amplified signals by the power amplifier to improve (e.g., expand) a frequency bandwidth of the power amplifier. As such, the power amplifier may have improved frequency bandwidth compared to other power amplifiers.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: September 8, 2026
    Assignee: Apple Inc.
    Inventor: Ahmed G Radwan
  • Patent number: 12732163
    Abstract: In accordance with a first aspect of the present disclosure, a tunable attenuator is provided, comprising: one or more transformer windings configured to facilitate attenuating a signal; one or more conductive loops provided underneath the transforming windings; a controller configured to control an amount of current flowing through the conductive loops, thereby providing a tunable attenuation of said signal. In accordance with a second aspect of the present disclosure, a corresponding method of producing a tunable attenuator is conceived.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: September 8, 2026
    Assignee: NXP B.V.
    Inventors: Pierre Pascal Savary, Mohamad El Ozeir, Stephane Damien ThuriƩs
  • Patent number: 12732143
    Abstract: A dual-drive power amplifier (PA) where the PA core includes a differential pair of transistors M1 and M2 that are driven by a coupling network having two transmission-line couplers, where a first transmission line section of a coupler is configured to transmit an input signal Vin through to drive a gate of the opposite transistor, while the second transmission line section is grounded at one end and coupled with the first transmission line section such that a coupled portion ?Vin of the input signal Vin drives the source terminal of a corresponding transistor. The arrangement of the coupling network allows the source terminals to be driven below ground potential. Embodiments disclosed here further provide an input matching network, a driver, an inter-stage matching network, and an output network for practical implementation of the PA core.
    Type: Grant
    Filed: July 3, 2024
    Date of Patent: September 8, 2026
    Assignee: Georgia Tech Research Corporation
    Inventors: Edgar Felipe Garay, Hua Wang
  • Patent number: 12726157
    Abstract: A power control apparatus comprises a voltage conversion circuit and a power control circuit, wherein the voltage conversion circuit is used for converting a power control voltage and outputting a target control voltage; and the power control circuit is connected to the voltage conversion circuit and is used for performing power control on a received input signal according to the target control voltage, so as to obtain a target output signal. In this way, by means of the cooperation of a voltage conversion circuit and a power control circuit, a target control voltage performs power control on an input signal, such that the number of harmonic waves generated by a power amplifier during power back-off can be reduced, thereby improving the harmonic performance of the power amplifier.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: September 1, 2026
    Assignee: SMARTER MICROELECTRONICS (GUANG ZHOU) CO., LTD.
    Inventors: Qiang Su, Chifeng Liu, Jiangtao Yi
  • Patent number: 12719410
    Abstract: The present disclosure provides a method and device for digital signal compensation. The method for signal compensation includes: generating a digital compensation signal at least partially based on smoothing, in real time, a digital input signal or a signal that is derived from the digital input signal; delaying the digital input signal such that the delayed digital input signal is aligned with the digital compensation signal in the time domain; and generating a digital compensated signal by combining the delayed digital input signal with the digital compensation signal.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: August 25, 2026
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Weixuan Hu
  • Patent number: 12719411
    Abstract: A high-speed amplifier circuit may include a first bias conversion circuit configured to perform a level-down operation on an input positive differential signal, a second bias conversion circuit configured to perform a level-up operation on an input negative differential signal, a first transmission circuit electrically connected to the first bias conversion circuit and configured to output a first differential signal having a voltage of a level within a first range among all levels, based on the positive differential signal on which the level-down operation has been performed, and a second transmission circuit electrically connected to the second bias conversion circuit and configured to output a second differential signal having a voltage of a level within a second range among all the levels, based on the negative differential signal on which the level-up operation has been performed.
    Type: Grant
    Filed: January 11, 2024
    Date of Patent: August 25, 2026
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Jaeduk Han, Sangwan Lee
  • Patent number: 12719418
    Abstract: A signal processing device is configured to compensate for process and temperature variations deviating from a nominal process and temperature condition. A transconductance amplifier circuit produces a current output dependent on a voltage input and a transconductance gain. A transimpedance amplifier circuit produces a voltage output dependent on the current. A bias circuit comprises transistors (M1, M2) configured such that the gate and drain of the first transistor (M1) are connected to the gate of the second transistor (M2) and to a PTAT current source. The source of the first transistor (M1) is connected to a node via a first resistor (R1), and the source of the second transistor (M2) is connected to that node via a second, trimmable resistor (R2). A feedback circuit for the transimpedance amplifier comprises a third, trimmable resistor (R3). The ratio between a resistance of the second and third resistors (R2, R3) is constant.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: August 25, 2026
    Assignee: Nordic Semiconductor ASA
    Inventor: Dominik Przyborowski
  • Patent number: 12719422
    Abstract: This disclosure is directed to a power amplifier (PA) including circuitry to amplify and filter transmission signals in a radio frequency (RF) circuit. The PA may include multiple core amplifiers coupled to a power combiner to amplify and filter the transmission signals. For example, the PA may activate the core amplifiers to provide the transmission signals with a peak output power. Alternatively, the PA may activate a reduced number of the core amplifiers to provide the transmission signals with a reduced output power lower than the peak output power. Activating a portion of the PA when providing the transmission signals with a reduced output power may reduce a power consumption and improve power efficiency of the PA.
    Type: Grant
    Filed: February 7, 2023
    Date of Patent: August 25, 2026
    Assignee: Apple Inc.
    Inventor: Simone Gambini
  • Patent number: 12712512
    Abstract: A low-voltage high-speed programmable equalization circuit includes a gain boosting amplifier stage, a CML differential amplifier stage, and an emitter follower. An input terminal of the gain boosting amplifier stage serves as an input terminal of the equalization circuit. An output terminal of the gain boosting amplifier stage is connected to an input terminal of the CML differential amplifier stage. An output terminal of the CML differential amplifier stage is connected to an input terminal of the emitter follower. An output terminal of the emitter follower serves as an output terminal of the equalization circuit.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: August 18, 2026
    Assignee: XIAMEN UX IC CO., LTD.
    Inventors: Faming Li, Yonghui Lin, Ming Hong
  • Patent number: 12712499
    Abstract: A power amplifier module includes a carrier circuit including at least one carrier amplifier; a peak circuit including at least one peak amplifier; a carrier control circuit that controls base current or gate voltage of a certain carrier amplifier in the carrier circuit; and a carrier output circuit that is connected to a carrier amplifier at an output side in the carrier circuit and that supplies a carrier control signal for controlling the base current or the gate voltage of the certain carrier amplifier to the carrier control circuit.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: August 18, 2026
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shohei Imai, Satoshi Tanaka
  • Patent number: 12712496
    Abstract: An amplifier circuit of the present disclosure includes: an input circuit that is configured to generate a differential current including a first current and a second current on the basis of an input signal; a first loop filter including a first former-stage integration circuit, a first inverter circuit, and a first latter-stage integration circuit, the first former-stage integration circuit configured to perform an integral action on the basis of the first current and a current corresponding to a first output signal, and the first latter-stage integration circuit that is configured to generate a first signal by receiving an output signal of the first inverter circuit and the first output signal and performing an integral action; a first modulation circuit; a first output circuit; a second loop filter including a second former-stage integration circuit, a second inverter circuit, and a second latter-stage integration circuit, the second former-stage integration circuit that receives the second current and a c
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: August 18, 2026
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Eiichi Nakamoto
  • Patent number: 12712501
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for radio frequency (RF) low noise amplifier (LNA) circuit configured to receive an input RF signal from an RF input source and provide an amplified output RF signal, where the RF LNA circuit includes an amplifier circuit, where the amplifier circuit is configured to receive the input RF signal and provide the amplified output RF signal, and an inductor-degenerated transconductor input impedance circuit that is separate from the amplifier circuit and that is operatively coupled to the input of the amplifier circuit.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: August 18, 2026
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: William Roeckner, Terrie McCain, Matthew Miller
  • Patent number: 12695431
    Abstract: In some embodiments, a method for operating a radio-frequency amplifier can include providing a bias signal to an amplifier implemented between an input node and an output node, and generating a detected voltage representative of a peak of a radio-frequency signal present at the input node. The method can further include enabling a protection mode when the detected voltage is greater than a first threshold value and disabling the protection mode when the detected voltage is less than a second threshold value that is less than the first threshold value.
    Type: Grant
    Filed: January 29, 2024
    Date of Patent: July 28, 2026
    Assignee: Skyworks Solutions, Inc.
    Inventor: Paul Raymond Andrys
  • Patent number: 12689336
    Abstract: An amplifier system includes an input pad having an input shunt capacitance, an output pad having an output shunt capacitance, and a high frequency amplifier including an input terminal coupled to the input pad and an output terminal coupled to the output pad. The input shunt capacitance is greater than the output shunt capacitance.
    Type: Grant
    Filed: June 25, 2023
    Date of Patent: July 21, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kunal Mahaseth, Hsieh-Hung Hsieh
  • Patent number: 12689335
    Abstract: This disclosure is directed to a programmable power amplifier including an output impedance matching circuit, and a programmable inductance matching circuit. The inductance matching circuit may be coupled to the impedance matching circuit. The inductance matching circuit may include one or more shunt inductors to reduce an adverse effect of one or more capacitors of the programmable power amplifier. The inductance matching circuit may improve an output power of the power amplifier, adjust a center frequency (e.g., resonant frequency) for providing output signals by the power amplifier, or both. As such, an electronic device may include one or more power amplifiers having the inductance matching circuit to amplify input signals with improved output power, improve a bandwidth for providing the output signals based on adjusting the center frequency, or both.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: July 21, 2026
    Assignee: Apple Inc.
    Inventor: Ahmed G Radwan
  • Patent number: 12689343
    Abstract: A transimpedance amplifier includes: a first operational amplifier; a second operational amplifier; a first resistor coupled between a first input terminal of the first operational amplifier and a first output terminal of the first operational amplifier; a second resistor coupled between the first output terminal of the first operational amplifier and a first input terminal of the second operational amplifier; and a first capacitor-resistor-capacitor (CRC) network coupled between the first input terminal of the second operational amplifier and a first output terminal of the second operational amplifier, where the first CRC network is a first reconfigurable filter that is configured to function as a first-order high-pass filter or a second-order high-pass filter based on a first control signal applied to the first CRC network.
    Type: Grant
    Filed: August 21, 2023
    Date of Patent: July 21, 2026
    Assignee: Infineon Technologies AG
    Inventor: Peter Unterkircher
  • Patent number: 12689333
    Abstract: A protection circuit for the power amplifier includes a detection circuit, a controller and an input impedance adjustment circuit. The detection circuit is provided with an input end connected to the power amplifier and an output end connected to an input end of the controller, and is configured to detect an operation electrical signal of the power amplifier and generate a trigger electrical signal. The controller is configured to generate a first control signal and a second control signal, the first control signal is configured to control a bias current or bias voltage of the power amplifier to reduce or recover a gain of the power amplifier, and the second control signal is configured to adjust characteristic parameters of the input impedance adjustment circuit. The input impedance adjustment circuit is configured to decrease or increase input power of the power amplifier in response to the second control signal.
    Type: Grant
    Filed: September 17, 2023
    Date of Patent: July 21, 2026
    Assignee: SMARTER MICROELECTRONICS (GUANG ZHOU) CO., LTD.
    Inventors: Yangyang Peng, Yang Hou
  • Patent number: 12683564
    Abstract: An integrated circuit includes a first substrate having a first substrate material, and the first substrate includes a first circuit. A second substrate has a second substrate material different than the first substrate material, and the second substrate includes a second circuit. A conductive interconnect electrically connects the first circuit and the second circuit.
    Type: Grant
    Filed: May 19, 2023
    Date of Patent: July 14, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Ling Chang, Hsieh-Hung Hsieh, Tzu-Jin Yeh
  • Patent number: 12683567
    Abstract: An input stage circuit for an operational amplifier includes first and second differential pairs connected in parallel between positive and negative input terminals. Each differential pair comprises a pair of transistors that are intentionally and systematically mismatched. The mismatching of each transistor pair creates a pre-trim input offset voltage for the circuit. However, a unique current is utilized to bias each of the first and second differential pairs. By adjusting the differential between the bias currents, a composite input offset voltage is created that combines with the pre-trim input offset voltage to yield a total input offset voltage for the circuit that approaches zero. Additionally, adjusting the differential between the bias currents simultaneously trims the temperature coefficient of the total input offset voltage to zero while using limited power and producing minimal noise.
    Type: Grant
    Filed: September 20, 2023
    Date of Patent: July 14, 2026
    Assignee: ZJW MICROELECTRONICS NORTH AMERICA INC.
    Inventors: Xiaoqiang Shou, Ziqing Lu
  • Patent number: 12671371
    Abstract: A fully differential power amplifier has an input matching network, a plurality of stacked transistors connected by a plurality of inter stack networks (ISNs), and an output matching network for amplification and conditioning of signal components. The differential amplifier uses a modified cascode FET topology with the FETs connected by gate decoupling capacitors to strongly attenuate common mode oscillations and eliminate the need for a source degeneration inductor or matching transformer. Inter stack networks provide signal conditioning and filtering between amplification stages to improve amplifier performance metrics such as long-term reliability, output power, and efficiency.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: June 30, 2026
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Mehdi Naseri Ali Abadi, Hassan Sarbishaei, Mostafa Azizi