Patents Examined by Henry Choe
  • Patent number: 11152903
    Abstract: In accordance with one embodiment, an apparatus includes a first amplifier having a noninverting input, an inverting input and an output. The noninverting input is coupled to a first ground reference. The inverting input is coupled to an output of an external sensor. The apparatus also includes a second amplifier having a noninverting input, an inverting input and an output. The noninverting input is coupled to the first ground reference. The inverting input is coupled to the power supply through a first variable capacitor and to the second ground reference through a second variable capacitor. The output is coupled to the inverting input of the first amplifier. The external sensor is coupled to a third ground reference, and the first amplifier and second amplifier are coupled to the second ground reference.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: October 19, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nagesh Surendranath, Shriram Mahendra Devi, Sravana Kumar Goli
  • Patent number: 11146216
    Abstract: A filter includes M filter circuits. The M filter circuits are sequentially cascaded from an input terminal to an output terminal, in order to generate an output signal according to an input signal, in which M is a positive integer greater than or equal to 2. The M filter circuits include at least one first filter circuit and at least one second filter circuit. Each of the at least one first filter circuit is set to be an active filter circuit, and each of the at least one second filter circuit is set to be a passive filter circuit.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: October 12, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Wei-Chen Lin, Hsuan-Yi Su, Chih-Lung Chen
  • Patent number: 11146217
    Abstract: A signal amplifier circuit having high power supply rejection ratio includes: a pre-amplifier which generates a driving signal at a driving control node; and a driving circuit which converts an input power to an output power. The driving circuit includes: a driving transistor, having a first terminal coupled to the input power and a second terminal coupled to the output power; and a power rejection circuit which includes a noise selection circuit. When the driving transistor operates in its linear region, the power rejection circuit senses an AC component of a power noise of the input power to generate an operation noise signal. The power rejection circuit generates the power rejection signal in AC form according to the operation noise signal to reject the power noise so as to increase the power supply rejection ratio.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: October 12, 2021
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Min-Hung Hu
  • Patent number: 11139788
    Abstract: A measuring current generation circuit coupled to a setting resistor is disclosed. The generation circuit includes a first measuring terminal, a second measuring terminal, a first transconductance amplifier, a second transconductance amplifier and an output circuit. The first transconductance amplifier has a first input terminal and a second input terminal. The first input terminal is coupled to one terminal of the setting resistor. The second input terminal is coupled to another terminal of the setting resistor and coupled to the first measuring terminal. The second transconductance amplifier has a third input terminal and a fourth input terminal. The output circuit is coupled to output terminals of the first transconductance amplifier and the second transconductance amplifier respectively and has a first output terminal and a second output terminal. The first output terminal is coupled to the first input terminal. The second output terminal is coupled to the second measuring terminal.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: October 5, 2021
    Assignee: UPI SEMICONDUCTOR CORP.
    Inventors: Yi-Xian Jan, Chien-Hsien Tsai, Kuo-Jen Kuo, Chao-Chung Huang, Chien-Kuei Chan
  • Patent number: 11139789
    Abstract: Chopper amplifiers with tracking of multiple input offsets are disclosed herein. In certain embodiments, a chopper amplifier includes chopper amplifier circuitry including an input chopping circuit, an amplification circuit, and an output chopping circuit electrically connected along a signal path. The amplification circuit includes two or more pairs of input transistors, from which a control circuit chooses a selected pair of input transistors to amplify an input signal. The chopper amplifier further incudes an offset correction circuit that senses the signal path to generate an input offset compensation signal for the amplification circuit. Furthermore, the offset correction circuit separately tracks an input offset of each of the two or more pairs of input transistors.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: October 5, 2021
    Assignee: Analog Devices, Inc.
    Inventor: Yoshinori Kusuda
  • Patent number: 11139786
    Abstract: An amplifying device includes a current generating circuit, a bias amplifying circuit, and a compensation circuit. The current generating circuit is configured to generate an internal current based on an internal voltage. The bias amplifying circuit, connected to the current generating circuit, is configured to output a bias current generated by amplifying the internal current to a power amplifying circuit. The compensation circuit, connected to the current generating circuit, is configured to adjust the internal voltage based on a bias voltage of the power amplifying circuit.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: October 5, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Je Hee Cho, Kyu Jin Choi
  • Patent number: 11133783
    Abstract: A power amplifier may comprise: an element for amplifying an electrical signal received through an input terminal, and outputting the amplified electrical signal through an output terminal; a first impedance adjustment circuit connected to the input terminal of the element and adjusting impedance with respect to a frequency of a fundamental component at the input terminal; a second impedance adjustment circuit connected to the input terminal of the element and adjusting impedance with respect to a frequency of a multiplied harmonic component at the input terminal; a third impedance adjustment circuit connected to the output terminal of the element and adjusting impedance with respect to the frequency of the fundamental component at the output terminal; a fourth impedance adjustment circuit connected to the output terminal of the element and adjusting impedance with respect to the frequency of the multiplied harmonic component at the output terminal; a first frequency separation circuit which prevents an imped
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: September 28, 2021
    Inventors: Sung-Ku Yeo, Bum-Man Kim, Yun-Sik Park, Sang-Wook Kwon, Dong-Gyu Min, Sung-Bum Park
  • Patent number: 11133786
    Abstract: Disclosed are a radiofrequency power amplifier module having high linearity and power-added efficiency and an implementation method. The radiofrequency power amplifier module comprises a bias circuit, a linearization circuit, and a power amplifier circuit. The power amplifier circuit is connected to the linearization circuit. The linearization circuit is connected to the bias circuit. The bias circuit is connected to the power amplifier circuit. In the present invention, the linearization circuit is utilized to capture a radiofrequency signal inputted from a radiofrequency signal input end of the power amplifier circuit, the captured radiofrequency signal is fed back to the bias circuit, a corresponding bias current is generated by the bias circuit on the basis of the radiofrequency signal fed back, and the bias current is inputted to the power amplifier circuit, thus increasing the linearity and power-added efficiency of an output signal of the radiofrequency power amplifier.
    Type: Grant
    Filed: July 1, 2018
    Date of Patent: September 28, 2021
    Assignee: VANCHIP (TIANJIN) TECHNOLOGY CO., LTD.
    Inventors: Gang Chen, Yunfang Bai
  • Patent number: 11128263
    Abstract: A temperature compensation circuit comprises a temperature coefficient circuit that generates a temperature coefficient that is temperature dependent and a compensation circuit that generates a compensation signal based on an indication of temperature of an amplifier and the temperature coefficient, and based on the compensation signal, a gain of the amplifier is adjusted to improve amplifier linearity during data bursts.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: September 21, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Gordon Glen Rabjohn, Edward John Wemyss Whittaker, Grant Darcy Poulin
  • Patent number: 11128268
    Abstract: Power amplifier (PA) packages containing peripherally-encapsulated dies are provided, as are methods for fabricating such PA packages. In embodiments, a method for fabricating a PA package includes obtaining a die-substrate assembly containing a radio frequency (RF) power die, a package substrate, and a die bond layer. The die bond layer is composed of at least one metallic constituent and electrically couples a backside of the RF power die to the package substrate. A peripheral encapsulant body is formed around the RF power die and covers at least a portion of the die bond layer, while leaving at least a majority of a frontside of the RF power die uncovered. Before or after forming the peripheral encapsulant body, terminals of the PA package are interconnected with the RF power die; and a cover piece is bonded to the die-substrate assembly to enclose a gas-containing cavity within the PA package.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: September 21, 2021
    Assignee: NXP USA, Inc.
    Inventors: Sharan Kishore, Jaynal A. Molla, Lakshminarayan Viswanathan, Tianwei Sun, David James Dougherty
  • Patent number: 11128269
    Abstract: An amplifier includes a driver stage amplifier transistor and a final stage amplifier transistor, which are integrated in a semiconductor die. The driver stage amplifier transistor has a driver stage input, a driver stage output, and an output impedance, and the driver stage amplifier transistor is configured to operate using a first bias voltage at the driver stage output. The final stage amplifier transistor has a final stage input, a final stage output, and an input impedance. The final stage input is electrically coupled to the driver stage output. The final stage amplifier transistor is configured to operate using a second bias voltage at the final stage output, and the second bias voltage is at least twice as large as the first bias voltage.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: September 21, 2021
    Assignee: NXP USA, Inc.
    Inventors: Elie A. Maalouf, Yu-Ting David Wu, Lu Wang, Nick Yang
  • Patent number: 11128272
    Abstract: Disclosed are a dual-path analog-front-end (AFE) circuit and a dual-path signal receiver characterized by high linearity. The dual-path AFE circuit includes a first reception circuit, a second reception circuit and a multiplexer. The first reception circuit is configured to generate a first analog input signal according to a reception signal in a first mode and configured to be coupled to a first constant-voltage terminal via a first switch circuit in a second mode. The second reception circuit is configured to generate a second analog input signal according to the reception signal in the second mode and configured to be coupled to a second constant-voltage terminal via a second switch circuit in the first mode. The multiplexer is configured to output the first analog input signal in the first mode and output the second analog input signal in the second mode.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 21, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Chien-Ming Wu
  • Patent number: 11128265
    Abstract: A communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) are provided. The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. An amplifier includes a first transistor for amplifying the fundamental signal applied to a gate terminal, and a second transistor having a source terminal electrically connected to the drain terminal of the first transistor and a drain terminal electrically connected to a bias voltage. The current flowing through the second transistor may be determined based on the current flowing in the drain terminal of the first transistor.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 21, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngchang Yoon, Kyuhwan An, Jihoon Kim, Sangho Lee
  • Patent number: 11121684
    Abstract: A device for digital envelope tracking with dynamically changing voltage levels for a radio frequency (RF) power amplifier is disclosed. A power management unit generates a set of supply voltages for a power amplifier based on a control signal. A setpoint generator in the power management integrated circuit gradually increases or decreases a target voltage such that the set of supply voltages output from the voltage converter gradually increase or decrease in response to a gradual transition of the target voltage. A transceiver includes digital models for replicating a behavior of the setpoint generator and a voltage regulator in the voltage converter such that a signal pre-distortion unit may use an instantaneous voltage level for signal predistortion.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: September 14, 2021
    Assignee: Apple Inc.
    Inventors: Stephan Henzler, Andreas Langer, Otto Schumacher
  • Patent number: 11121677
    Abstract: Provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor Cc, an amplifier load capacitor CL, a reference current source Iref and a PMOS transistor M0 that provides a constant current source function. Further provided in the present invention is a transconductance amplifier based on a self-biased cascode structure, which adopts an NMOS transistor as an input transistor.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: September 14, 2021
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Daiguo Xu, Gangyi Hu, Ruzhang Li, Jian'an Wang, Guangbing Chen, Yuxin Wang, Tao Liu, Lu Liu, Minming Deng, Hanfu Shi, Xu Wang
  • Patent number: 11121681
    Abstract: Bias circuitry is disclosed with a bias drive device having a first current terminal coupled to a voltage supply node, a bias control terminal coupled to a control node, and a second current terminal coupled to a bias output node. An impedance control device has a third current terminal and an impedance control terminal that are coupled together and a fourth current terminal coupled to ground. An output impedance resistor is coupled between the third current terminal and the bias output node. A pull-down device is coupled between the bias output node and the fixed voltage node, wherein a higher voltage applied to the control node sets an output impedance at the bias output node to approximately a lower impedance of the pull-down device and a lower voltage applied to the control node sets the output impedance to approximately the resistance of the output impedance resistor.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: September 14, 2021
    Assignee: Qorvo International PTE. LTD.
    Inventor: Michael Nielsen
  • Patent number: 11121689
    Abstract: A sensor failure prediction system is a sensor failure prediction system that predicts a failure of a physical quantity sensor including a vibrator element which is driven and vibrates by a drive signal and outputs a detection signal based on a physical quantity, and includes a memory that stores reference information on a reference value of the drive signal or the detection signal, and a processor that outputs prediction information on a stepwise or continuous state until the physical quantity sensor fails, based on signal information on a measurement value of the drive signal or the detection signal and the reference information.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: September 14, 2021
    Assignee: Seiko Epson Corporation
    Inventor: Chikara Nakayama
  • Patent number: 11114981
    Abstract: Disclosed is a differential amplifier including an input circuit, a detecting and controlling circuit, and an output circuit. The input circuit outputs input current to two output nodes according to the voltage of a differential input signal and the voltage of a bias node. The detecting and controlling circuit outputs compensative current to the two output nodes according to control bias voltage and the voltage of the bias node, in which the voltage of the bias node and the compensative current relate to the voltage of the differential input signal. The output circuit is coupled to the two output nodes and outputs a differential output signal according to the sum of the input current and the compensative current. Due to the detecting and controlling circuit outputting the compensative current, the differential amplifier prevents itself from entering a deadlock state even though the input current is insufficient or zero.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: September 7, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Tzung-Ling Tsai, Shu-Lin Chang, Chih-Lung Chen
  • Patent number: 11114987
    Abstract: The present disclosure relates to a switchable power amplification structure including a first power amplifier (PA), a second PA, a front switching structure, and an end switching structure. The front switching structure is coupled to a radio frequency (RF) input port, and the end switching structure is coupled to an antenna port. Herein, the first PA and the second PA are parallel to each other, each of which is coupled between the front switching structure and the first end switching structure. The front switching structure is configured to selectively couple the first PA and the second PA to the RF input port, while the end switching structure is configured to selectively couple the first PA and the second PA to the first antenna port.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: September 7, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Carsten Hinrichsen, Søren Deleuran Laursen
  • Patent number: 11114985
    Abstract: A high frequency amplifier 1 includes an input terminal PIN, an output terminal POUT, a transistor 5 configured to amplify an RF signal applied to the input terminal PIN, a matching circuit 9 for a fundamental of the RF signal and a reflection circuit 7 for a harmonic relative to the fundamental, the matching circuit 9 and the reflection circuit 7 being connected in series between the transistor 5 and the output terminal POUT, an extraction circuit 13 configured to extract a harmonic appearing at the output terminal POUT, processing circuits 15, 17 configured to adjust a phase and intensity of the harmonic extracted by the extraction circuit 13, and a multiplexing circuit 19 configured to multiplex the harmonic processed by the processing circuits 15, 17 to the harmonic reflected by the reflection circuit 7 and give the multiplexed harmonic to the transistor 5.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: September 7, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Yuji Kimoto