Abstract: An amplifier system includes an input pad having an input shunt capacitance, an output pad having an output shunt capacitance, and a high frequency amplifier including an input terminal coupled to the input pad and an output terminal coupled to the output pad. The input shunt capacitance is greater than the output shunt capacitance.

Abstract: This disclosure is directed to a programmable power amplifier including an output impedance matching circuit, and a programmable inductance matching circuit. The inductance matching circuit may be coupled to the impedance matching circuit. The inductance matching circuit may include one or more shunt inductors to reduce an adverse effect of one or more capacitors of the programmable power amplifier. The inductance matching circuit may improve an output power of the power amplifier, adjust a center frequency (e.g., resonant frequency) for providing output signals by the power amplifier, or both. As such, an electronic device may include one or more power amplifiers having the inductance matching circuit to amplify input signals with improved output power, improve a bandwidth for providing the output signals based on adjusting the center frequency, or both.

Abstract: A transimpedance amplifier includes: a first operational amplifier; a second operational amplifier; a first resistor coupled between a first input terminal of the first operational amplifier and a first output terminal of the first operational amplifier; a second resistor coupled between the first output terminal of the first operational amplifier and a first input terminal of the second operational amplifier; and a first capacitor-resistor-capacitor (CRC) network coupled between the first input terminal of the second operational amplifier and a first output terminal of the second operational amplifier, where the first CRC network is a first reconfigurable filter that is configured to function as a first-order high-pass filter or a second-order high-pass filter based on a first control signal applied to the first CRC network.

Abstract: A protection circuit for the power amplifier includes a detection circuit, a controller and an input impedance adjustment circuit. The detection circuit is provided with an input end connected to the power amplifier and an output end connected to an input end of the controller, and is configured to detect an operation electrical signal of the power amplifier and generate a trigger electrical signal. The controller is configured to generate a first control signal and a second control signal, the first control signal is configured to control a bias current or bias voltage of the power amplifier to reduce or recover a gain of the power amplifier, and the second control signal is configured to adjust characteristic parameters of the input impedance adjustment circuit. The input impedance adjustment circuit is configured to decrease or increase input power of the power amplifier in response to the second control signal.

Abstract: An integrated circuit includes a first substrate having a first substrate material, and the first substrate includes a first circuit. A second substrate has a second substrate material different than the first substrate material, and the second substrate includes a second circuit. A conductive interconnect electrically connects the first circuit and the second circuit.

Abstract: An input stage circuit for an operational amplifier includes first and second differential pairs connected in parallel between positive and negative input terminals. Each differential pair comprises a pair of transistors that are intentionally and systematically mismatched. The mismatching of each transistor pair creates a pre-trim input offset voltage for the circuit. However, a unique current is utilized to bias each of the first and second differential pairs. By adjusting the differential between the bias currents, a composite input offset voltage is created that combines with the pre-trim input offset voltage to yield a total input offset voltage for the circuit that approaches zero. Additionally, adjusting the differential between the bias currents simultaneously trims the temperature coefficient of the total input offset voltage to zero while using limited power and producing minimal noise.

Abstract: A fully differential power amplifier has an input matching network, a plurality of stacked transistors connected by a plurality of inter stack networks (ISNs), and an output matching network for amplification and conditioning of signal components. The differential amplifier uses a modified cascode FET topology with the FETs connected by gate decoupling capacitors to strongly attenuate common mode oscillations and eliminate the need for a source degeneration inductor or matching transformer. Inter stack networks provide signal conditioning and filtering between amplification stages to improve amplifier performance metrics such as long-term reliability, output power, and efficiency.

Abstract: Amplitude modulation-phase modulation (AM-PM) linearization in a power amplifier using bias circuitry, which fixes a bias of a cascode transistor within a power amplifier is disclosed. In particular, the cascode transistor may switch between operation in a saturation mode and a triode mode. The bias is set such that the cascode transistor operates at a fixed duty cycle in the triode mode relative to the saturation mode for a wide range of signal levels from small-signal to large-signal. An exemplary duty cycle is fifty percent (50%), although other duty cycles may be used. This bias will result in a constant capacitance contributed by the cascode device to the power amplifier over a wide signal level range.

Abstract: A method and system for producing an adjustable resistor with a set resistance for adjusting quiescent current in a GaN transistor in a power amplifier. A quiescent current on the GaN power amplifier is measured via a test probe from a microcontroller unit on a test fixture. A resistance value is determined for output of a voltage bias value to adjust the quiescent current of the GaN transistor in the power amplifier. The resistance value is stored in an electronically adjustable resistor. The adjustable resistor is coupled to an output voltage circuit to provide voltage at the voltage vias value to a voltage bias input of the power amplifier.

Abstract: Disclosed is an operational amplifier circuit and a switching circuit. The operational amplifier circuit comprises a main operational amplifier, which performs operational amplification based on a reference signal and a feedback signal of an output voltage of the switching circuit to obtain an operational amplification signal for controlling a switching state of the switching circuit, and generates an adjustment signal according to the feedback signal, the reference signal, and a preset first voltage. When a load of the switching circuit is reduced, an output terminal of the main operational amplifier receives the adjustment signal and obtains an adjusted operational amplification signal, and the adjustment signal is used for suppressing a change of the operational amplification signal.

Abstract: A tracker module is provided that includes a substrate, a tracker component, a filter, a first output terminal, and a second output terminal. The first output terminal is disposed on a second main surface of the substrate and is connected to a first power amplifier. The second output terminal is disposed on the second main surface of the substrate and is connected to a second power amplifier. The first output terminal is connected to the tracker component via the filter. The second output terminal is connected to the tracker component. The first output terminal overlaps a rectangular region in a plan view in a thickness direction of the substrate that encompasses an inductor and a capacitor of the filter.

Abstract: Disclosed is a radio frequency power amplifier that reduces load change sensitivity, which comprises a feedback circuit (10) and a plurality of levels of amplification circuit, the feedback circuit (10) and all or a portion of amplification circuit among the plurality of levels of amplification circuit being connected in parallel between a first node (M) and a second node (N), and a feedback loop made up of the feedback circuit (10) and an amplification circuit main path located between the first node (M) and the second node (N) forming a 180°+360°×n phase shift, where n is a natural number.

Abstract: A continuous time op-amp includes a differential op-amp configured to produce, and output through output lines, output signals amplified based on a difference between input signals inputted to the differential op-amp, and a common mode feedback (CMFB) circuit configured to feed a common mode voltage back to the op-amp through a feedback line in continuous time through a capacitive coupled path, wherein the CMFB circuit includes: feedback capacitors connected between the output lines and the feedback line; switched capacitors charged based on a common mode reference voltage; and switching elements configured to control a connection between the feedback capacitors and the switched capacitors.

Abstract: There are included a first amplifier and a second amplifier electrically connected to a stage subsequent to the first amplifier, a third amplifier and a fourth amplifier electrically connected to a stage subsequent to the third amplifier, a phase shifter that makes a phase of a radio-frequency signal passing through a first path different from a phase of a radio-frequency signal passing through a second path, a first bias circuit that supplies a bias to the first amplifier and the third amplifier, a second bias circuit that supplies a bias to the first amplifier and the second amplifier, and a third bias circuit that supplies a bias to the third amplifier and the fourth amplifier. The second amplifier includes a second transistor, the fourth amplifier includes a fourth transistor, the second bias circuit includes a sixth transistor, and the third bias circuit includes a seventh transistor.

Abstract: This disclosure provides systems, methods, and devices for wireless communications that support multiple antenna operation. In a first aspect, an apparatus for wireless communications includes an amplifier module comprising a first input node, a second input node, a first output node, a second output node, and a third output node, with the amplifier comprising a first processing path configured to couple the first input node to the first output node; and a second processing path configured to couple the second input node to the second output node in a first mode and to couple the second input node to the third output node in a second mode. Other aspects and features are also claimed and described.

Abstract: Provided is a physical quantity outputting circuit including a first output terminal, a power supply terminal to which an external power supply voltage is input, a reference terminal to which a reference voltage is input, a power supply voltage circuit which generates an internal power supply voltage from the external power supply voltage, a first output amplifier to which a first input signal corresponding to the physical quantity sensing result is input and which outputs the first output voltage corresponding to the first input signal to the first output terminal, a first resistor connected between the power supply terminal and the first output terminal, and a second resistor connected between the first output terminal and the reference terminal. In the physical quantity outputting circuit, current that flows from the power supply voltage circuit to the first output amplifier has a constant value.

Abstract: A differential signaling circuit is provided. The differential signaling circuit includes: a differential amplifier configured to generate differential signals; a first signal path circuit; a second signal path circuit; a phase control circuit configured to receive the differential signals having a common phase, output DC signals having a common level in a first operating period, and transmit the differential signals to the first signal path circuit and the second signal path circuit, respectively, in a second operating period; and a duty ratio correction circuit connected between the first signal path circuit and the second signal path circuit, and configured to control duty ratios of the differential signals to be equal to each other in the second operating period.

Abstract: Wireless circuitry can include a radio-frequency amplifier, a power detection circuit coupled to an output of the radio-frequency amplifier and configured to output a power detection voltage, protection circuitry coupled to the power detection circuit and configured to output a protection voltage, and a control circuit configured to adjust the amplifier based on the power detection voltage and the protection voltage. The protection circuitry can include a current mirroring circuit that outputs a current proportional to a supply current of the power detection circuit and an adjustable current-to-voltage converter such as an adjustable resistor that receives the current to generate the protection voltage.

Abstract: In some embodiments, a power amplifier circuit can include a power amplifier having an input node and an output node, and a load modulation circuit coupled to the output node of the power amplifier. The power amplifier circuit can further include a control profile configured to provide information for generating a control signal for the load modulation circuit, and a control circuit configured to generate and provide the control signal to the load modulation circuit based on the control profile. In some embodiments, the control profile can be further configured to provide information for generating a control signal for a phase compensation circuit.

Abstract: A low-noise amplifier is disclosed having a first transistor with a first current terminal coupled to a supply voltage rail through a load resistor and a second current terminal coupled to an input node, wherein a bias resistor is coupled between the input node and a fixed voltage node. A second transistor has a third current terminal coupled to an output node and a fourth current terminal coupled to the fixed voltage node. A feedback capacitor is coupled between the input node and the output node, wherein capacitance of the feedback capacitor is sized to eliminate the need for coupling an input impedance matching inductor to the input node.