Patents Examined by Henry Choe
  • Patent number: 10812025
    Abstract: Radio frequency (RF) amplifier circuitry includes an input node, an output node, an amplifier, and bootstrap circuitry. The amplifier includes a control node coupled to the input node, a first amplifier node coupled to the output node, and a second amplifier node coupled to a fixed potential. The amplifier is configured to receive an input signal having a first frequency at the control node and change an impedance between the first amplifier node and the second amplifier node based on the input signal. The bootstrap circuitry is coupled between the control node and the second amplifier node. The bootstrap circuitry is configured to provide a low impedance path between the control node and the second amplifier node for signals having a second frequency that is equal to about twice the first frequency and provide a high impedance path for signals having a frequency outside the second frequency.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 20, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Marcus Granger-Jones, George Maxim, Jinsung Choi
  • Patent number: 10812027
    Abstract: An isolation circuit and a method for providing isolation between two dies are provided. The isolation circuit includes: an isolation module, configured to generate an isolation signal based on an input signal from a first die and to provide isolation between the first die and a second die, where the isolation signal is smaller than the input signal in amplitude, and the first die is coupled with the second die; a latch module, configured to latch the isolation signal at a certain level and output a latched signal; an amplifier module, configured to amplify the latched signal. In the isolation circuit, a modulation module and a demodulation module can be saved.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 20, 2020
    Assignee: 2PAI SEMICONDUCTOR CO., LIMITED
    Inventor: Zhiwei Dong
  • Patent number: 10804852
    Abstract: To provide a high-voltage output amplifier having a wide bandwidth which can efficiently reduce power consumption and allows employment of relatively low withstand voltage Nch MOS FETs without imbalanced voltage distribution between a Nch MOS FET Q101 and a Nch MOS FET Q102 and imbalanced distribution between a Nch MOS FET Q201 and a Nch MOS FET Q202. A high-voltage amplifier of a positive-side output stage circuit comprises a Nch MOS FET Q101 and a Nch MOS FET Q102, while a high-voltage amplifier of a negative-side output stage circuit comprises a Nch MOS FET Q201 and a Nch MOS FET Q 202. The source of the Nch MOS FET Q101 is connected to the drain of the Nch MOS FET Q102, the source of the Nch MOS FET Q201 is connected to the drain of the Nch MOS FET Q202. Current controls at the source of the Nch MOS FET Q102 and the source of the Nch MOS FET Q202 are conducted respectively. The current control at the source of the Nch MOS FET Q202 is conducted by a negative-side photo coupler.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 13, 2020
    Inventor: Masaki Ogura
  • Patent number: 10804882
    Abstract: A hybrid multiplexer includes a filter configured to allow a high-frequency signal of an HB to pass therethrough, and a filter configured to allow a high-frequency signal of an MB to pass therethrough, in which the filter includes a matching circuit, a first resonance circuit defined by one of an LPF and an HPF, and a second resonance circuit defined by the other of the LPF and the HPF, the LPF includes an inductor and a parallel arm resonator, the HPF includes a serial arm resonator and an inductor, and a resonant frequency of the parallel arm resonator and an anti-resonant frequency of the serial arm resonator are both located between a frequency at a low-band end of the HB and a frequency at a high-band end of the HB.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: October 13, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiroshi Matsubara, Masanori Kato, Syunsuke Kido
  • Patent number: 10797664
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for a chopper instrumentation amplifier. For a variety of applications, such as testing the resistance of connections between layers of a memory, it may be desirable to provide a high gain instrumentation amplifier. A chopper instrumentation amplifier may provide a high gain while allowing a wide range of common input voltages and a canceling an offset on the amplifier. An example chopper instrumentation amplifier of the present disclosure may include a plurality of amplifiers including chopper amplifiers and non-chopper amplifiers. The chopper amplifiers may use chopper circuits to cancel out an offset voltage of the amplifiers. Low pass filters may be used to minimize the impact of the chopper amplifiers.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Akira Ide
  • Patent number: 10797659
    Abstract: According to an aspect, an audio amplifier includes a first sigma-delta modulator configured to receive a digital audio signal and generate a first multi-level output signal based on the audio signal, and a second sigma-delta modulator configured to receive the first multi-level output signal from the first sigma-delta modulator and generate a second multi-level output signal. The second multi-level output signal has a number of levels less than a number of levels of the first multi-level output signal.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: October 6, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIED, LLC
    Inventor: Christian Venanzi Caduff
  • Patent number: 10790786
    Abstract: Systems, methods, and circuitries are provided for generating a power amplifier supply voltage based on a target envelope signal for a radio frequency (RF) transmit signal. An envelope tracking system includes a first selector circuitry and predistortion circuitry. The first selector circuitry is disposed in a selector module and is configured to input a plurality of voltages conducted on a first plurality of power lanes, wherein the first plurality of power lanes is part of a power distribution network; select a voltage from the plurality of voltages based on the target envelope signal; and provide the selected voltage to a supply lane connected to an input of the power amplifier that amplifies the RF transmit signal. The predistortion circuitry is configured to modify the RF transmit signal based on a selected power lane of the first plurality of power lanes that conducts the selected voltage.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Stephan Henzler, Andreas Langer, Bernhard Raaf
  • Patent number: 10784819
    Abstract: Apparatus and methods for power amplifiers with positive envelope feedback are provided herein. In certain implementations, a power amplifier system includes a power amplification stage that amplifies a radio frequency signal, at least one envelope detector that generates one or more detection signals indicating an output signal envelope of the power amplification stage, and a wideband feedback circuit that provides positive envelope feedback to a bias of the power amplification stage based on the one or more detection signals. The power amplifier system further includes a supply modulator that controls a voltage level of a supply voltage of the power amplification stage based on the one or more detection signals such that the supply voltage is modulated with the output signal envelope through positive envelope feedback.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 22, 2020
    Inventors: Smarjeet Sharma, Nicolas Gerard Constantin
  • Patent number: 10771020
    Abstract: A circuit that outputs a current which is proportional to an input voltage includes input and output terminals, a comparator, first and second transistors, an inductor, a first resistor, and a differential amplifier. A first input terminal of the comparator is coupled to the input terminal of the circuit, and a second input terminal of the comparator is coupled to an output terminal of the comparator. The first and second transistors are coupled to the output terminal of the comparator. The inductor is coupled to the first and second transistors. The first resistor is coupled between the inductor and the output terminal of the circuit. The differential amplifier includes a first input terminal coupled to a first terminal of the first resistor, a second input terminal coupled to a second terminal to the first resistor, and an output terminal coupled to the first input terminal of the comparator.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: September 8, 2020
    Assignee: Fluke Corporation
    Inventors: William J. Britz, Jake R. Richards
  • Patent number: 10771022
    Abstract: Embodiments of the present disclosure provide circuitry and a method for a gallium nitride (GaN) device. The circuitry includes a negative bias circuit configured to provide a negative bias voltage for a gate of the GaN device; a drain switch circuit configured to turn on or off a positive voltage for a drain of the GaN device; and a control circuit configured to control the drain switch circuit based on provision of the negative bias voltage, such that the positive voltage for the drain is turned on after a voltage of the gate reaches the negative bias voltage and turned off before the negative bias voltage completely disappears.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: September 8, 2020
    Assignee: Alcatel Lucent
    Inventors: Baoliang Feng, Jingjing Shi, Zaiqing Li
  • Patent number: 10771021
    Abstract: A system for thermally protecting an amplifier driving a capacitive load may include a low-pass filter configured to filter, with a variable cutoff frequency, an input signal to generate a filtered input signal, wherein the amplifier is configured to receive the filtered input signal and amplify the filtered input signal to generate a driving signal to the capacitive load and a controller configured to receive a real-time estimate of a temperature associated with the amplifier and vary the variable cutoff frequency as a function of the temperature.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: September 8, 2020
    Assignee: Cirrus Logic, Inc.
    Inventor: Eric Lindemann
  • Patent number: 10771025
    Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: September 8, 2020
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Patent number: 10763803
    Abstract: An integrated circuit includes a die that includes a circuit configured to generate a PWM signal in response to a first clock signal, and a first set of pads configured to provide amplified PWM signals to external filters. An amplifier stage is configured to provide the amplified PWM signals. The die includes two pads configured to be coupled to an external inductor, and a second set of pads configured to provide regulated voltages. An electronic converter circuit is configured to generate the regulated voltages to supply the amplifier stage. The electronic converter circuit includes a control circuit configured to drive electronic switches in response to a second clock signal to regulate the regulated voltages to a respective target value. The die includes a control block to synchronize the switching activity of the electronic switches with the switching activity of the amplifier stage.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: September 1, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Edoardo Botti, Tommaso Barbieri, Davide Luigi Brambilla, Cristiano Meroni
  • Patent number: 10763228
    Abstract: Devices including a transistor having a parasitic capacitance between a control terminal and a load terminal of a first type are provided. Furthermore, the devices include advantageously arranged inductances which are electromagnetically coupled to one another and are configured at least partly to compensate for an effect of the parasitic capacitance in a range around a resonant frequency.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 1, 2020
    Assignee: Infineon Technologies AG
    Inventors: David Seebacher, Andrea Del Chiaro, Peter Singerl, Ji Zhao
  • Patent number: 10763801
    Abstract: An amplification device is configured to operate such that when a first amplifier function is switched to a second amplifier function (S13) and then the second amplifier function is switched to the first amplifier function (S15) and at this time a state of an operating member is a state corresponding to a second sound volume larger than a first sound volume that was output right before switching from the first amplifier function to the second amplifier function (S16), the amplification device causes the state of the operating member to change to a state corresponding to a third sound volume smaller than the second sound volume (S17), and controls an amplifying operation of a signal processing circuit to cause it to output the third sound volume (S18).
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: September 1, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Satomi Ito, Masaaki Tomoda, Yoshifumi Inoue
  • Patent number: 10756687
    Abstract: System controller and method for providing at least an output voltage. For example, the system controller includes a first controller terminal configured to receive an input voltage. The input voltage is associated with an input-voltage magnitude. Additionally, the system controller includes a second controller terminal configured to receive a control voltage, and a third controller terminal configured to output an output voltage to a load. Moreover, the system controller includes a supply voltage generator configured to receive the input voltage from the first controller terminal and generate a supply voltage. The supply voltage is associated with a supply voltage magnitude. Also, the system controller includes a ramp voltage generator configured to receive the supply voltage and generate a ramp voltage.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 25, 2020
    Assignee: On-Bright Electronics (Shanghai) Co., Ltd.
    Inventors: Miao Li, Qiang Luo, Lieyi Fang
  • Patent number: 10756677
    Abstract: Doherty power amplifier having high supply voltage. In some embodiments, a power amplification system can include a supply system configured to provide a high-voltage supply signal, and a Doherty power amplifier having an input splitter configured to receive and split a signal into a carrier amplifier and a peaking amplifier. The Doherty power amplifier can further include a combiner configured to combine amplified signals from the carrier and peaking amplifiers to provide an output signal. The Doherty power amplifier can be configured to receive the high-voltage supply signal for operation of the carrier and peaking amplifiers. The power amplification system can further include an output path configured to couple the combiner to a filter. The Doherty power amplifier can have an impedance substantially the same as an impedance of the filter when operated with the high-voltage supply signal.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: August 25, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventor: Philip John Lehtola
  • Patent number: 10749474
    Abstract: A switching circuit includes a switching circuit stage configured to supply a load via filter networks. Control circuitry is provided to control alternate switching sequences of transistors in the half-bridges of the switching circuit stage. A current flow line is provided between the output nodes of the half-bridges including an inductance between two switches. First and second capacitances are coupled with the output nodes of the half-bridges. The control circuitry switches first and second switches to the conductive state at intervals in the alternate switching sequences of the transistors in the half-bridges between switching the first pair of transistors to a non-conductive state and switching the second pair of transistors to a conductive state.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: August 18, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Edoardo Botti, Giovanni Gonano
  • Patent number: 10749476
    Abstract: A tracker circuit configured to provide a variable supply voltage to a power amplifier (PA) circuit is disclosed. The tracker circuit includes a state machine circuit comprising a plurality of states mapped in accordance with transitions associated with a mapping scheme. In some embodiments, the plurality of states of the state machine circuit identify one or more operational modes associated with the tracker circuit, wherein at least one operational mode comprises one or more voltage levels respectively associated therewith. In some embodiments, the one or more operational modes includes at least two active operational modes. In some embodiments, a transition between the one or more operational modes of the tracker circuit is controlled by a digital selection signal received from a digital communication interface associated therewith.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: August 18, 2020
    Assignee: Intel IP Corporation
    Inventors: Ilan Sutskover, Eran Segev, Stephan Henzler, Alexander Belitzer
  • Patent number: 10749478
    Abstract: An amplifier arrangement (200) for amplifying input signals and a method for operating the amplifier arrangement are disclosed. The amplifier arrangement (200) comprises a main amplifier circuit (210) having an input and an output; a first (221) and second (222) auxiliary amplifier circuits each having an input and an output, wherein each of the first (221) and second (222) auxiliary amplifier circuits being selectively operable to operate in combination with the main amplifier circuit (210). The amplifier arrangement (200) further comprises a single hybrid coupler circuit (230) having a first port (221) being coupled to the output of the main amplifier circuit (210), a second port (232) being coupled to the output of the first auxiliary amplifier circuit (221), a third port (233) being coupled to the output of the second auxiliary amplifier circuit (222) and a fourth port (234) being coupled to the load (240) of the amplifier (200).
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: August 18, 2020
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Rui Hou, Andre Bleker, Lars Ridell Virtanen