Patents Examined by Henry Choe
  • Patent number: 11870402
    Abstract: Aspects of this disclosure relate to an impedance transformation circuit for use in an amplifier, such as a low noise amplifier. The impedance transformation circuit includes a matching circuit including a first inductor. The impedance transformation circuit also includes a second inductor. The first and second inductors are magnetically coupled to each other to provide negative feedback to linearize the amplifier.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: January 9, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventor: Leslie Paul Wallis
  • Patent number: 11870202
    Abstract: Methods and apparatus for processing a substrate. For example, a processing chamber can include a power source, an amplifier connected to the power source, comprising at least one of a gallium nitride (GaN) transistor or a gallium arsenide (GaAs) transistor, and configured to amplify a power level of an input signal received from the power source to heat a substrate in a process volume, and a cooling plate configured to receive a coolant to cool the amplifier during operation.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: January 9, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Rajesh Kumar Putti, Vinodh Ramachandran, Ananthkrishna Jupudi, Lean Wui Koh, Prashant Agarwal
  • Patent number: 11863128
    Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor that supplies a bias current based on a first current which is a part of a control current to the first transistor; a current output element in which a current flowing therethrough increases in accordance with a rise in temperature; and a wiring portion including a plurality of metal layers that are electrically connected to an emitter of the first transistor and that are stacked one on top of another so as to oppose the semiconductor substrate. At least one metal layer among the plurality of metal layers extends so as to overlap an area extending from at least a part of a first disposition area in which the first transistor is disposed to a second disposition area in which the current output element is disposed in plan view of the semiconductor substrate.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: January 2, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hideyuki Sato, Koshi Himeda
  • Patent number: 11863130
    Abstract: RF transistor amplifiers include a Group III nitride-based RF transistor amplifier die that includes a semiconductor layer structure, a conductive source via that is connected to a source region of the Group III nitride-based RF transistor amplifier die, the conductive source via extending through the semiconductor layer structure, and an additional conductive via that extends through the semiconductor layer structure. A first end of the additional conductive via is connected to a first external circuit and a second end of the additional conductive via that is opposite the first end is connected to a first matching circuit.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: January 2, 2024
    Assignee: Wolfspeed, Inc.
    Inventors: Basim Noori, Marvin Marbell, Qianli Mu, Kwangmo Chris Lim, Michael E. Watts, Mario Bokatius, Jangheon Kim
  • Patent number: 11850046
    Abstract: A simplified electronics approach to allow cost, size, and power consumption to be reduced while maintaining state of the art accuracy and reliability, key features for wireless medical devices/systems. Extreme accuracy is achieved by innovative noise shaping and filtering introduced to the electrochemical sensor, before sampling by the analog to digital converter. Introduction of the noise to the electrochemical sensor provides very low power biasing which is necessary to achieve overall reliable and very accurate bias for the electrochemical reaction cell.
    Type: Grant
    Filed: February 27, 2021
    Date of Patent: December 26, 2023
    Inventors: Robert Bruce Ganton, Robert S Ballam
  • Patent number: 11855596
    Abstract: An amplifier circuit includes a first input unit, a second input unit, a first current supply unit, and a second current supply unit. The first input unit changes a voltage level of a first output node based on a first input signal. The second input unit changes a voltage level of a second output node based on a second input signal. The first current supply unit supplies a first current to the first output node based on a voltage level of the first output node and boosts the voltage level of the first output node for a predetermined time when the voltage level of the first output node is changed. The second current supply unit supplies a second current to the second output node based on the voltage level of the first output node.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: December 26, 2023
    Assignee: SK hynix Inc.
    Inventor: Kyu Dong Hwang
  • Patent number: 11855589
    Abstract: A low-noise amplifier in a receiver supporting a beam forming function may selectively change a phase shift for beam steering. The low-noise amplifier may include first and second transistors and a variable capacitance circuit connected to a gate of the second transistor. The variable capacitance circuit may selectively change capacitance thereof based on a capacitance control signal applied thereto according to beam-forming information, where the changed capacitance correspondingly causes a phase change in an output signal of the low-noise amplifier. A similar scheme may be employed for amplifiers in transmit signal paths to steer a transmit beam.
    Type: Grant
    Filed: June 28, 2020
    Date of Patent: December 26, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-min Kim, Jae-seung Lee, Jung-seok Lim, Pil-sung Jang
  • Patent number: 11855587
    Abstract: A power amplifier circuit includes an amplifier transistor that amplifies an input signal, a resistance element coupled in series with the base of the amplifier transistor, a bias transistor that supplies a bias current from the emitter or the source of the bias transistor to the base of the amplifier transistor through the resistance element, and a feedback circuit that changes a base or gate voltage of the bias transistor to follow a change in the bias current supplied to the base of the amplifier transistor.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: December 26, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takashi Soga
  • Patent number: 11855586
    Abstract: A power amplifier module includes an amplifier transistor and a bias circuit. A first power supply voltage based on a first operation mode or a second power supply voltage based on a second operation mode is supplied to the amplifier transistor. The amplifier transistor receives a first signal and outputs a second signal obtained by amplifying the first signal. The bias circuit supplies a bias current to the amplifier transistor. The bias circuit includes first and second resistors and first and second transistors. The first transistor is connected in series with the first resistor and is turned ON by a first bias control voltage which is supplied when the first operation mode is used. The second transistor is connected in series with the second resistor and is turned ON by a second bias control voltage which is supplied when the second operation mode is used.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: December 26, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masao Kondo, Hidetoshi Matsumoto
  • Patent number: 11848650
    Abstract: A differential power amplifier includes an input matching network, a first-stage amplification circuit, a first inter-stage matching network, a second-stage amplification circuit, a second inter-stage matching network, a third-stage amplification circuit, and an output matching network. The first-stage amplification circuit and the second-stage amplification circuit are single-ended input single-ended output circuits. The third-stage amplification circuit is a dual input dual output circuit. The second inter-stage matching network includes a first transformer T1, a first capacitor C1, a second capacitor C2, a first inductor L1, and a second inductor L2. The output matching network includes a second transformer T2. The inter-stage matching networks and the output matching network are realized by the first transformer T1 and the second transformer T2, which reduces an inter-stage matching difficulty, optimizes input return loss and gain, and improves output power.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: December 19, 2023
    Assignee: LANSUS TECHNOLOGIES INC.
    Inventors: Zhiyuan Xie, Yuting Zhao, Jiashuai Guo
  • Patent number: 11848653
    Abstract: A system to control convergence of a loop to a reference value. A device, under control of the control loop, generates an output signal. A comparator compares the output signal to a reference value. Responsive to the output signal being less than the reference value, outputting an up signal and, responsive to the output signal being greater than the reference value, outputting a down signal. A counter is configured to maintain a counter value which is incremented in response to an up signal and decremented in response to a down signal. The counter outputs a gain control value. An up/down signal tracker is configured to track a pattern of up signals and down signals and compare the tracked pattern to one or more predetermined patterns such that, responsive to the up signals and down signals matching one of the one or more predetermined patterns, the counter size is decreased.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: December 19, 2023
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Vasilis Papanikolaou, George L. Barrier, IV
  • Patent number: 11843352
    Abstract: Apparatus and methods for an inverted Doherty amplifier operating at gigahertz frequencies are described. RF fractional bandwidth and signal bandwidth may be increased over a conventional Doherty amplifier configuration when impedance-matching components and an impedance inverter in an output network of the inverted Doherty amplifier are designed based on characteristics of the main and peaking amplifier and asymmetry factor of the amplifier.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: December 12, 2023
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Christian Cassou, Gerard Bouisse
  • Patent number: 11837997
    Abstract: Disclosed examples include differential amplifier circuits and variable neutralization circuits for providing an adjustable neutralization impedance between an amplifier input node and an amplifier output node, including neutralization impedance T circuits with first and second impedance elements in series between the amplifier input and output, and a third impedance element, including a first terminal connected to a node between the first and second impedance elements, and a second terminal connected to a transistor. The transistor operates according to a control signal to control the neutralization impedance between the amplifier input node and the amplifier output node.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: December 5, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Krishnanshu Dandu, Brian P. Ginsburg
  • Patent number: 11837998
    Abstract: A gain compression compensation circuit of a radio frequency power amplifier includes: a low-pass filtering module configured to receive a part of radio frequency signals output from a first power amplification transistor and to filter, from the part of radio frequency signals, radio frequency signals with a frequency above a fundamental wave to obtain a filtered signal; and a rectifying module configured to receive the filtered signal output by the low-pass filtering module and to rectify the filtered signal to obtain a rectified current; and to output the rectified current to a bias transistor and superimpose the rectified current with a bias current Ibias to flow into the bias transistor.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: December 5, 2023
    Assignee: SMARTER MICROELECTRONICS (GUANG ZHOU) CO., LTD.
    Inventors: Jiangtao Yi, Qiang Su, Huadong Wen
  • Patent number: 11831280
    Abstract: Methods and circuital arrangements for turning OFF branches of a multi-branch cascode amplifier are presented. First and second switching arrangements coupled to a branch allow turning OFF the branch while protecting transistors of the branch from a supply voltage that may be greater than a tolerable voltage of the transistors. The first switching arrangement includes a transistor-based switch that is in series connection with the transistors of the branch. The first switching arrangement drops the supply voltage during the OFF state of the branch and provides a conduction path for a current through the branch during the ON state of the branch. A resistor and a shunting switch are coupled to a gate of the transistor-based switch to reduce parasitic coupling effects of the transistor-based switch upon an RF signal coupled to the branch during the ON state and OFF state of the branch.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: November 28, 2023
    Assignee: PSEMI CORPORATION
    Inventors: Miles Sanner, Emre Ayranci, Parvez Daruwalla
  • Patent number: 11824501
    Abstract: A power amplifier circuit includes a first amplifier that, in a region where an input signal level is a first level or higher, amplifies a signal split from an input signal and outputs an amplified signal; a first converter connected to an output side of the first amplifier and converts an impedance on the output side of the first amplifier; and at least one or more second amplifiers that, in a region where the input signal level is a second level or higher, amplify a signal split from the input signal and output an amplified signal. Output sides of the second amplifiers are connected in series with an output side of the first converter. The first converter makes an absolute value of the impedance on the output side of the first amplifier larger than absolute values of impedances on the output sides of the second amplifiers.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: November 21, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shohei Imai
  • Patent number: 11824500
    Abstract: An apparatus is disclosed for waveform-tailored average power tracking. In an example aspect, the apparatus includes an amplifier, a power converter, and an average power tracking module. The amplifier is configured to amplify radio-frequency signals using a supply voltage. The radio-frequency signals have different waveforms. The power converter is coupled to the amplifier and configured to provide the supply voltage. The average power tracking module is coupled to the power converter and configured to adjust the supply voltage according to the different waveforms to cause the supply voltage to vary across at least two waveforms of the different waveforms for related average output powers.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: November 21, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Xiangdong Zhang, Ryan Scott Castro Spring, Marco Cassia, Yan Kit Gary Hau, Kanan Gandhi, Robert Wilson
  • Patent number: 11824502
    Abstract: Systems comprising a low power Digital Predistortion (DPD) system and methods of operation thereof are disclosed herein. In some embodiments, a system comprises a DPD system for digitally predistorting an input signal to provide an output signal. The DPD system comprises a DPD actuator comprising one or more configurable multiplication functions, each configurable to operate in different power modes. The different power modes comprise a first power mode in which the configurable multiplication function multiplies a first value related to an input sample of the input signal and a second value related to a respective DPD value to provide an output value and a second power mode in which the configurable multiplication function outputs, as the output value, are an approximation of a multiplication of the first value and the second value.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: November 21, 2023
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Kristian Eklund, Asad Jafri, Jessica Chani
  • Patent number: 11817832
    Abstract: A semiconductor-on-insulator die can include a power amplifier configured to amplify a radio frequency input signal having a fundamental frequency. The die can further include an output matching circuit including first and second second-order harmonic rejection circuits configured to resonate at about two times the fundamental frequency and a third order harmonic rejection circuit configured to resonate at about three times the fundamental frequency.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: November 14, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Yang Liu, Yong Hee Lee, Thomas Obkircher, William J. Domino
  • Patent number: 11817836
    Abstract: A power amplifying module includes a first input terminal, a second input terminal, a first power amplifier, a stage matching circuit, a bypass line, and a second power amplifier. The first input terminal receives a first input signal in a first operation mode. The second input terminal receives a second input signal in a second operation mode which is different from the first operation mode. The first power amplifier amplifies the first input signal and outputs a first amplified signal. The stage matching circuit is disposed downstream of the first power amplifier and receives the first amplified signal. The bypass line outputs the second input signal to the inside of the stage matching circuit not through the first power amplifier. The second power amplifier is disposed downstream of the stage matching circuit, and amplifies the first amplified signal or the second input signal and outputs a second amplified signal.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: November 14, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshiaki Sukemori, Kenji Tahara, Hideyuki Sato, Hisanori Namie