Abstract: A regulator with decreased leakage and low loss for a power amplifier is described. Switching circuitry is used to connect the regulator input bias to a bias control voltage when the power amplifier is to be operated in an on condition or to a voltage generator when the power amplifier is to be operated in an off condition.

Abstract: Techniques for generating a bias voltage for a class AB amplifier having first and second active transistors. In an exemplary embodiment, a diode-coupled first transistor supports a first current, and the gate voltage of the first transistor is coupled to the gate voltage of the first active transistor. The first current is split into a second current and a first auxiliary current supported by a second transistor, which is biased at a desired common-mode output voltage of the class AB amplifier. The first auxiliary current is further combined with a third current to be supported by a third transistor, with the third transistor configured to replicate the characteristic of the second active transistor. Further techniques are provided for setting the drain voltage of the third transistor to be close to the common-mode output voltage. The techniques described herein may be used to provide a bias voltage for the NMOS and/or PMOS active transistors in a class AB amplifier.

Abstract: A circuit, system and method determine the control voltage for a DC-DC converter. A control module determines a raw battery voltage and an operating temperature. It references a look up table to determine a voltage regulator control voltage based on the battery voltage and the operating temperature during normal operation. In some cases, the control module also uses a level of interference to determine the control voltage.

Abstract: An amplifying device (10) includes first, second, third and fourth transistors (M1, M2, M3, M4). In the first and third transistors (M1, M3) the source is connected to an input signal source (IN+, IN?), the gate is connected to a biasing potential (VB) and the drain is connected to a signal output (O+, O?). There is a first and second branch (B1, B2) between the source and drain of the first and third transistor (M1, M3), respectively, each including a corresponding second or fourth transistor (M2, M4). The device also includes a third branch (B3) comprising a first capacitor (C1) and a first switch (SW1) connected between the first transistor (M1) source and the third transistor (M3) gate, and a fourth branch (B4) comprising a second capacitor (C2) and a second switch (SW2) connected between the third transistor (M3) source and the first transistor (M1) gate.

Abstract: An output stage for an amplifier is provided. The amplifier generally provides for compensation of an error current generated by the base-collector (or gate-drain) capacitance of a common base (or gate) amplifier transistor. The stage accomplishes this by utilizing a three transistor Wilson current mirror to combine the error current with a mirrored bias current to reduce the load current on the common base (or gate) amplifier transistor.

Abstract: A driving circuit of enhancing response speed is disclosed. The driving circuit includes an operational amplifier and a slew rate enhancement unit. The operational amplifier is utilized for generating a driving voltage according to an input voltage. The slew rate enhancement unit is coupled to the operational amplifier, and is utilized for generating a compensation current to the operational amplifier to enlarge a bias current of the operational amplifier according to voltage difference between the input voltage and the driving voltage when variation of the input voltage occurs.

Abstract: A calibration device for a power amplifier includes a calculation unit, a first storage unit and a multiplier. The calculation unit is utilized for generating a calibration factor according to a value of a characteristic parameter of the power amplifier. The first storage unit coupled to the calculation unit, for storing the calibration factor. The multiplier is coupled to the first storage unit and a baseband unit, for multiplying a baseband signal outputted from the baseband unit by the calibration factor for generating an input signal to the power amplifier.

Abstract: Methods and systems are disclosed for predictive feedback compensation (PFC) circuitry for suppressing distortions caused by supply voltage variations and output amplitude switching non-idealities in pulse width modulated (PWM) switching amplifiers by pre-compensating the PWM input based upon the supply voltage or output pulse amplitude. Output amplitude errors associated with previous PWM output signals are used to predict output amplitude errors expected for future PWM output signals. These predicted output amplitude errors are then used to adjust the pulse widths for the future PWM output signals. Traditional feedback techniques can also be used in conjunction with the predictive feedback compensation (PFC) circuitry.

Abstract: Systems and methods for characterizing amplifiers. A system for characterizing an amplifier in accordance with the present invention comprises a Gaussian signal source for generating a signal in the frequency domain, a notch filter, coupled to the Gaussian Noise source, wherein the notch filter has a notch at a specified frequency and a frequency bandwidth, the frequency bandwidth encompassing the specified frequency, an Inverse Fast Fourier Transform device, coupled to an output of the notch filter, a normalization device, coupled to the Inverse Fast Fourier Transform device, an amplifier under test, coupled to the normalization device, for amplifying the signal generated by the Gaussian signal source, and a measurement device, coupled to an output of the amplifier, for measuring a power output of the amplifier in the frequency bandwidth and a noise output at the specified notch frequency, and for calculating the ratio between the power output and the noise output.

Abstract: A hybrid power control system (102) that selectively applies voltage-based gain control and current-based gain control and method (300) of controlling a power amplifier (104) gain are presented. A voltage-based gain control signal (120) is applied to control the gain of the power amplifier when a level output power is indicated by a power contour signal (132). Whether the power amplifier is saturated is identified. A current-based gain control signal (122) is applied to control the gain of the power amplifier when the power amplifier is saturated and a decrease in output power is indicated by the power contour signal.

Abstract: An operational amplifier includes a differential amplifier including an active load, a current mirror including a first branch and a second branch, a first switch connected between a first power source and an output node and switched in response to a voltage of a first output terminal of the differential amplifier, a first bias circuit to control an amount of a reference current flowing in the first branch in response to a voltage of a second output terminal of the differential amplifier, a second bias circuit to control a voltage of the second branch in which a mirror current flows, in response to a voltage of the first output terminal, a second switch connected between the output node and a second power source and switched in response to a voltage of the second branch, and a capacitor connected between the output node and the first output terminal.

Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212).

Abstract: A cascoded current-mirror circuit includes a first N channel MOS transistor, a second N channel MOS transistor, a third N channel MOS transistor and a fourth N channel MOS transistor. The first N channel MOS transistor and the second N channel MOS transistor are cascode-connected between a higher voltage source and a lower voltage source. The third N channel MOS transistor and the fourth N channel MOS transistor are cascode-connected between the higher voltage source and the lower voltage source. A drain of the first N channel MOS transistor is connected to gates of the first N channel MOS transistor, the second N channel MOS transistor, the third N channel MOS transistor and the fourth N channel MOS transistor. The threshold voltages of the second N channel MOS transistor and the fourth N channel MOS transistor are larger than those of the first N channel MOS transistor and the third N channel MOS transistor.

Abstract: A sample-and-hold amplifier is provided. The sample-and-hold amplifier comprises a sample-and-hold circuit and a buffer circuit. The sample-and-hold circuit receives an input signal and transmits the input signal to a first node according to a control signal. The buffer circuit is coupled between a supply voltage source and a ground and controlled by the first node to provide an output signal at an output node. The buffer circuit comprises a native MOS transistor coupled to the output node.

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device, to provide a stable, low-noise output signal.

Abstract: Disclosed a power amplifier including a main amplifier with class bias AB and a peak amplifier with class C bias. A quarter-wave length transmission line having a length equal to one-fourth of the wave-length of a fundamental frequency is connected to an output side of the peak amplifier. Outputs of the main amplifier and the peak amplifier are combined. An envelope amplifier that modulates the drain bias voltage in accordance with an envelope of the modulation wave input signal and an envelope detector are provided as a drain-bias circuit for the main amplifier (FIG. 1).

Abstract: A description is provided of a high-frequency, multi-stage, millimeter wave amplifier integrated circuit, and of a method for designing and constructing the circuit. The methods and structures have been created to enable the construction of an amplifier offering substantial gain at a relatively high power and high frequency, but occupying minimal area of an integrated circuit die. Various structures and methodologies are described which each contribute to the practical feasibility of constructing an amplifier with such performance in a relatively compact space.

Abstract: A two stage fully differential amplifier has been designed which works, in tandem with a TX-FIR, as a linear equalizer at low frequencies, not covered by the TX-FIR, and also acts as a linear amplifier at higher frequencies which are equalized by the TX-FIR. The amplifier as a frequency response which does not attenuate signals frequencies less than one twentieth of baud rate, creates gain peaking ion the region between one twentieth and one tenth of baud rate and maintains flat peak gain up to half of baud rate. Different aspects of the frequency response curve (such as dc gain, max gain and zero frequency) are completely programmable. Also, the differential amplifier has been designed from low power and process, voltage and temperature insensitive frequency response.

Abstract: The present invention relates to a method for correcting for a source of non-linearity and noise introduced in a switching power amplification stage during power amplification of a pulse-modulated reference signal from a pulse modulator, where the method comprises the following steps: —providing an output stage embedded in an analogue self-oscillating control loop able to receive a pulse-referenced input signal; —generating a feedback signal from the switching power amplification stage or after a demodulation filter; —deriving an error signal by comparing the feedback signal with the reference signal; —filtering the error signal by a low pass filter for reducing the higher harmonics of the carrier; —adding a compensator for generating high loop gain in the audio band; —feeding the compensator output to a zero cross detector or comparator, thus providing a carrier for re-modulation or re-timing by feeding the filtered signal to a zero cross detector or comparator, which controls the output stage.

Abstract: A radio frequency signal is input to the bases of transistors via respective capacitors, is amplified, and is output from the collectors of the transistors. The emitter of each transistor is grounded. A bias current input from a bias circuit is supplied to the bases of the transistors via respective resistors both during low-output operation and during high-output operation. The collectors of the transistors are connected via an impedance circuit to a bias voltage input terminal. Therefore, during high-output operation, a direct current offset voltage is generated by the impedance circuit based on a portion of a radio frequency signal output from the collectors, thereby further increasing the bias current.