Abstract: A detuned composite amplifier includes a nonlinear drive function (22) that has a phase that varies with the composite amplifier output voltage amplitude. The nonlinear drive function (22) is configured to transform the output voltage transition point of the prior art into an extended output voltage transition region to increase the efficiency of the composite amplifier.

Abstract: Provided is a power amplification device including: a DC power supply that outputs a drain voltage; a Doherty amplifier including a carrier amplifier and a peak amplifier, which are connected in parallel, and amplifies an RF signal; a voltage control circuit that outputs a first instruction to output a low voltage when an output power is equal to or lower than a given value, and outputs a second instruction to output a high voltage when the output power is larger than the given value; and a voltage converter circuit that converts the drain voltage to a voltage lower than the drain voltage and applies the converted voltage to drain terminals of the carrier amplifier and the peak amplifier according to the first instruction, and applies the drain voltage directly to the drain terminals of the carrier amplifier and the peak amplifier according to the second instruction.

Abstract: A power added efficiency optimizer apparatus is provided for measuring and monitoring input and output power of an amplifying device, and adjusting the load impedance seen by the amplifying device so that power added efficiency is maintained at optimum levels. A power added efficiency optimizing device includes a variable load impedance that can be controlled, at least one power detection device located after the load, a difference forming apparatus, and at least one coupling device. The power added efficiency optimizing device provides an ability to maintain an amplifier at peak efficiency in a dynamic way and in the presence of changing electromagnetic load conditions.

Abstract: Common mode choke coil device includes four coils wound on a core in a same direction. Hot-side outputs of first and second class-D amplifiers are connected to respective ones of first ends of two of the four coils, and first and second hot-side output terminals are connected to respective ones of second ends of the two coils. Ground-side outputs of the first and second class-D amplifiers are connected to respective ones of the first ends of remaining two of the four coils, and first and second ground-side output terminals are connected to respective ones of the second ends of the remaining two coils. Single-end connection is realized by connecting a separate load to each of the class-D amplifiers via the corresponding first (or second) hot-side and ground-side output terminals. BTL connection is realized by connecting a single load to the class-D amplifiers via the first and second hot-side output terminals.

Abstract: A current canceling CMOS variable gain amplifier includes a first leg and a second leg. The first leg has a first input line, a first output line, a first ON transistor, a first control transistor and a first subtracting transistor. The second leg has a second input line, a second output line, a second ON transistor, a second control transistor and a second subtracting transistor. The second input line can provide a second input current. The second output line can provide a second output current. The first input line is arranged to provide a first input current to each of the first ON transistor, the first control transistor and the first subtracting transistor. The second input line is arranged to provide a second input current to each of the second ON transistor, the second control transistor and the second subtracting transistor. The first output line is in electrical connection with each of the first ON transistor, the first control transistor and the second subtracting transistor.

Abstract: Systems and methods for reduced distortion in a class D amplifier are provided. An “ideal” digital output signal is produced. The “ideal” digital output signal is then compared to the actual output signal in an error amplifier. The integrator input is the difference between the output stage waveform and the ideal output stage waveform. The net input to the integrator now comprises the imperfections of the power stage, and the feedback loop drives their average to zero. This error is then amplified and integrated. The integrated signal is than applied to a summer where it is added to the analog input. Then as in the typical Class D amplifier, the integrated signal is compared in an error amplifier to a ramp signal generated from the ramp generator.

Abstract: A programmable gain MOS amplifier is disclosed. The programmable gain MOS amplifier is capable of increasing its programmable gain linearly in dB unit by increasing its gain level data linearly. The programmable gain MOS amplifier includes a plurality of gain providers for providing predetermined gains respectively, and a plurality of gain tuners. Each of the plurality of the gain tuners is disposed for adjusting the predetermined gain from the corresponding gain provider. Each of the gain tuners includes a gain enabling module and a gain decreasing module. The gain enabling module allows the corresponding predetermined gain to add to the programmable gain of the MOS amplifier. The gain decreasing module declines the corresponding predetermined gain added to the programmable gain of the MOS amplifier.

Abstract: Operational amplifier embodiments are provided to enhance amplifier parameters such as bandwidth, stability, and headroom. In an amplifier embodiment, transistor followers are arranged with first and second differential pairs to facilitate selective positioning of first and second transfer function poles to enhance bandwidth and resistors and inductors are arranged to facilitate selective positioning of complex third transfer function poles to enhance phase margin. In another amplifier embodiment, the transistor followers are arranged to reduce headroom limitations to thereby enhance the voltage swing of output signals.

Abstract: An amplifier is provided with continuously-variable analog control that exhibits a highly linear gain control curve in db/volts, while preserving high dynamic range, low third order distortion, and low noise. This amplifier has a control mechanism that preserves a varied linear or log linear curve over a wide range and is inherently insensitive to process variations thereby allowing more accurate gain control and higher signal fidelity for amplifying high dynamic range signals.

Abstract: Systems, methods, and apparatuses are provided for linear envelope elimination and restoration transmitters that are based on the polar modulation operating in conjunction with the orthogonal recursive predistortion technique. The polar modulation technique enhances the battery life by dynamically adjusting the bias level. Further, the analog orthogonal recursive predistortion efficiently corrects amplitude and phase errors in radio frequency (RF) power amplifiers (PA) and enhances the PA output capability. Additionally, even-order distortion components are used to predistort the input signal in a multiplicative manner so that the effective correction bandwidth is greatly enhanced. Also, the predistortion scheme, which uses instantaneously feed-backed envelope distortion signals, allows for correction of any distortion that may occur within the correction loop bandwidth, including envelope memory effects.

Abstract: The present invention discloses a premium power amplifier applied in an antenna module, and the premium power amplifier includes a first transmission unit, having two symmetrical and identical first arc-shaped circuits, two secondary power amplifiers connected in parallel with each other, and a second transmission unit having two symmetrical and identical second arc-shaped circuits, in which those components above are installed between a power amplifier and an output terminal of the antenna. So that the output power of the antenna can be improved greatly, and the effective transmission distance can be extended.

Abstract: A differential amplifier circuit includes an offset adjuster circuit for varying the active load to adjust the offset caused by the differential pair. The differential amplifier circuit includes fine adjustment cell sections including a plurality of transistors having the substantially same size, and shift cell sections including transistors, whose transistor size is larger than the transistors of the fine adjustment cell sections.

Abstract: An amplifier which operates with low power is provided. In the amplifier, a first input unit includes a first control circuit and a second control circuit each including one terminal connected to an output node and the other terminal connected to a respective input transistor from among the plurality of input transistors, and controls the amount of current flowing into the plurality of input transistors or flowing out of the plurality of input transistors according to operating modes of the amplifier, whereby even when an A bias current is increased in order to increase a slew rate of the amplifier, a B bias current a the quiescent current do not increase.

Abstract: A wideband low-noise amplifier includes a source-degenerated common-source amplifier, a common-gate amplifier, and a matching frequency band determiner. The source-degenerated common-source amplifier is configured to amplify an input signal to output a first signal that is opposite in phase to the input signal. The common-gate amplifier is connected in parallel to the source-degenerated common-source amplifier to amplify the input signal to output a second signal that has the same phase as the input signal. The matching frequency band determiner is configured to isolate an input terminal of the source-degenerated common-source amplifier and an input terminal of the common-gate amplifier and determine a matching frequency band.

Abstract: A class G headphone amplifier circuit with improved power efficiency and low EMI. It may use an automatic signal level detector to detect the signal level of incoming signals and determine positive and negative power supplies for headphone amplifiers accordingly. A voltage generator may generate pairs of differential output voltages at a plurality of amplitude steps, and supply to headphone amplifiers the pair with the amplitude determined by the automatic signal level detector. As a result, headphone amplifiers are biased according to the input signal level, and the multiple voltage rails may improve power efficiency and avoid clipping.

Abstract: Embodiments include but are not limited to apparatuses and systems including a circuit comprising a unit cell including an input and an output, and a harmonic trap, intrinsic to the unit cell, implemented on one of the input and the output. Other embodiments may be described and claimed.

Abstract: A power amplifier bias circuit having a controllable current profile includes a first transistor device configured as a switch, and configured to receive a non-regulated system voltage, and a plurality of resistors configured to provide a current and configured to determine an amount of a bias current that flows through a second transistor device, where the second transistor device is part of a current mirror comprising a third transistor device and the amount of bias current flowing through the second transistor device determines a power output of the third transistor device.

Abstract: A level-shifting amplifier is provided for level-shifting an input signal with a voltage magnitude that exceeds a supply voltage of the amplifier. In operation, the amplifier has an input impedance of greater than 100 MOhms.

Abstract: An apparatus includes an electronic amplifier and an electrical feedback line, a plurality of electrical sources, and an electronic controller. The electrical feedback line connects an output of the electronic amplifier to an input thereof. The electrical sources connect to nodes on the electronic feedback line. The electronic controller is configured to adjust the electrical sources in a manner responsive to a current input to the electrical feedback line.

Abstract: It is an object of the present invention to provide a high-frequency power amplifier capable of improving the linearity at the time of high output by preventing decrease in power of bias supply transistor. The high-frequency power amplifier is a high-frequency power amplifier including high-frequency power amplifier transistors and connected in multiple stages and bias supply transistors and each of which supplies bias current to a base of a corresponding one of said high-frequency power amplifier transistors, and each of which is connected to a common power supply terminal which is further connected to a collector of the high-frequency power amplifier transistor at a first stage among said high-frequency power amplifier transistors, and a passive element connected between the common supply terminal and a collector of the corresponding one of said bias supply transistors connected to the high-frequency power amplifier transistor at the first stage.