Abstract: An amplifier includes: a class AB input stage, receiving an input signal, for generating an inner signal according to the input signal; class AB output stage, includes: a biasing circuit, for providing a first voltage and a second voltage according to the inner signal; and an output stage, for generating an output signal according to the first voltage and the second voltage; wherein a voltage difference between the first voltage and the second voltage generated by the biasing circuit is corresponding to the input signal.

Abstract: An amplifier comprises: first and second supply terminals intended to receive a DC supply voltage; a first branch coupled between the first and second supply terminals and including a first terminal of application of a differential signal to be amplified; a second branch coupled between the first and second supply terminals and including a second terminal of application of the differential signal to be amplified; a third branch coupled between the first and second supply terminals and including a first amplifier having an input terminal connected to the second branch and having an output terminal configured to be coupled to a load, and a measurement element configured to measure a current in the third branch; and a fourth branch coupled between the first and second supply terminals and including a second amplifier having an input terminal connected to the first branch, and a copying element configured to copy the current measured in the third branch.

Abstract: A plurality of analog signals are input to input terminals of an analog signal processing circuit ANA2 via respective capacitors C. In a bias circuit Bias for supplying a bias voltage such as a signal ground of the analog signals to the analog signal processing circuit ANA2, in an operational amplifier OpAS, a bias voltage VIr is input from a non-inverting input VIP of a built-in differentiate amplifier circuit, an output terminal of the built-in output amplifier circuit OA1 is connected to an inverting input terminal VIM of the differentiate amplifier circuit DA, and thereby a voltage follower is obtained. Furthermore, a plurality of output amplifier circuits OA2 through OAn are provided so that input terminals thereof are connected to output terminals of the differential amplifier circuit DA, and the output terminals are connected to input terminals IN1 through INn of the analog signal processing circuit ANA2.

Abstract: An amplifier provided according to an aspect of the present invention includes a set of passive impedances forming a tuned load to a gain stage and also to provide a 180 degrees phase shifted signal of a gain signal received from the gain stage. The output of the gain stage and the 180 degrees phase shifted signal together form a differential amplified signal corresponding to an input signal gained by the gain stage. In an embodiment, the set of passive impedances includes a three terminal centre tapped inductor in combination with a capacitor, together operating as a filter to pass only a desired frequency band. The windings of the inductor may be designed to provide mutual coupling between two portions such that there is a negative correlation between the strength of the received gained signal and the 180 degree phase shifted signal.

Abstract: According to some embodiments, an amplifier may include a transconductance stage, a tail current source stage, and an adaptive biasing stage. The transconductance stage may be configured to receive an input voltage. The tail current source stage may be configured to provide current to the transconductance stage. The adaptive biasing stage may capacitively couple the transconductance stage to the tail current source stage.

Abstract: A charge pump power supply for a consumer device audio power stage has an efficiency selected according to signal level. The frequency of operation of the charge pump and/or the effective size of a switching transistor bank is adjusted based upon a volume (gain) setting, or a detected signal level, so that internal power consumption of the charge pump is reduced when high output current is not required from the audio power stage and consequently from the charge pump. Operating modes of the charge pump are selected by the signal level indication and include at least a high power and a high efficiency mode selected by setting the charge pump operating frequency and/or enabling or disabling switching of one or more of multiple parallel transistors used to implement each switching element of the charge pump, thereby setting the level of gate capacitance being charged/discharged by the gate driver circuit(s).

Abstract: A differential amplifier circuit 110 composed of an inverter is connected to the power supply voltage VCC and the ground voltage GND through a NMOS transistor 142 and a PMOS transistor 144 respectively. The NMOS transistor 142 is connected to the control signal terminal PS, and the PMOS transistor 144 is connected to control signal terminal PS through an inverter 150. The NMOS transistor 142 and the PMOS transistor 144 are controlled such that they can be simultaneously cut off by a control signal from the control signal terminal PS. In this way, the power consumption of the amplifier is reduced.

Abstract: A common-base amplifier for a bipolar junction transistor or a heterojunction bipolar transistor employs an active current source output biasing to provide for improved power output in a power saturation region providing increased power for a given transistor area such as may be advantageous in mobile radio transmitters or the like.

Abstract: The present invention is aimed at realizing an amplifying circuit whose chip size is prevented from being significantly increased even if the number of compatible frequencies increases, and which has a wide dynamic range when it operates under a low voltage.

Abstract: Provided are a gain control device and an amplifier using the gain control device. The gain control device includes a first input resistance unit having a first variable resistor whose resistance is linearly variable and a first fixed resistor respectively receiving a first input signal and a second input signal having a sign different from the first input signal and outputting current through a first output terminal, and a second input resistance unit having a second fixed resistor and a second variable resistor whose resistance is linearly variable respectively receiving the first input signal and the second input signal and outputting current through a second output terminal. Since the gain control device can separately perform dB-linear gain control, it is easily combined with a circuit, such as a continuous-time sigma-delta modulator (SDM), a continuous-time filter, and a continuous-time analog-to-digital converter (ADC), and enables miniaturization and low power consumption.

Abstract: A composite differential Radio Frequency (RF) power amplifier includes a plurality of differential RF cascode power amplifiers coupled in parallel. Each differential RF cascode power amplifier includes a positive transconductance stage and a positive cascode stage coupled in series with the positive transconductance stage between a voltage node and ground. Each also includes a negative transconductance stage and a negative cascode stage coupled in series with the negative transconductance stage between the voltage node and ground.

Abstract: An output stage circuit is disclosed, which includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. By using twin-well CMOS transistors and a specific circuit configuration, the invention supports a HALF AVDD structure, reduces power consumption and saves the cost of triple-well CMOS process.

Abstract: The variable gain amplifier includes a bias circuit (BC) 1, a matching circuit (MC) 2, a variable gain resistive feedback amplifier (FA) 3 and an output follower (EA) 4. The resistance values of the load resistance Rc and feedback resistance Rf are changed in cooperation. In a case of making the load resistance Rc a high resistance to set the low noise amplifier to a high gain, the feedback resistance Rf is also made a high resistance, the feedback time constant ?fb(c1)?2?·RfCbe/(1+gmRc) of the closed loop of the resistive negative feedback amplifier 3 becomes substantially constant, and then the amplifier has a gain small in frequency dependency over a wide bandwidth. In a case of making the load resistance Rc a low resistance to set the low noise amplifier to a low gain, the feedback resistance Rf is also made a low resistance. The feedback resistance Rf with the low resistance increases the negative feedback quantity, and thus the amplifier is set to a low gain.

Abstract: A differential-pair amplifier comprising a transistor pair. The differential-pair amplifier includes a current source coupled to the transistor pair for providing a bias current to the transistor pair. The differential-pair amplifier also includes a switching mechanism coupled to the transistor pair for steering the bias current away from the transistor pair when disabling the amplifier operation. A system and method in accordance with the present invention allows fast enabling and disabling of a differential-pair amplifier. This fast switching technique can be used in the signal paths where the switching time is critical.

Abstract: The invention provides a switching audio power amplifier with de-noise function, including a first comparator, a second comparator, a logic control unit, a de-noise circuit, and a bridge circuit. The first comparator and the second comparator respectively generate the first PWM signal and the second PWM signal, and then the logic control unit performs logic operation to generate a third PWM signal and a fourth PWM signal. If the pulse width of the third PWM signal (or the fourth PWM signal) is lower than a threshold, the de-noise circuit increases the pulse width of the third PWM signal or the fourth PWM signal and outputs the fifth PWM signal and the sixth PWM signal to drive the bridge circuit. Next, the bridge circuit conducts a driving current alternately flowing to and from a load according to the firth PWM signal and the sixth PWM signal.

Abstract: A system and method of improving the power efficiency of a receiver for low duty cycle applications. In one aspect, the receiver includes a low noise amplifier (LNA) that is capable of being enabled in a relatively quick fashion so as to amplify an incoming signal when needed, and then being disabled to set the LNA in a low power consumption mode. In particular, the LNA includes a pair of complimentary devices, and an enable circuit adapted to quickly cause the complimentary devices to conduct substantially the same current. In another aspect, a bias voltage generating apparatus is provided that uses a residual voltage from a prior operation to establish the current bias voltage for the LNA. In particular, the apparatus includes a controller adapted to tune an adjustable capacitor to a capacitance based on a residual voltage applied to a fixed capacitor, and couple the capacitors together to establish the bias voltage.

Abstract: A low delay corrector (LDC) unit includes a non-linear function generator and a filter. The nonlinear function generator receives a first signal and outputs a second signal in dependence on the first signal and a transfer function of the nonlinear function generator. The filter is fed in dependence on the second signal output by the nonlinear function generator. The first signal received by the nonlinear function generator is derived in dependence on an input signal provided to an input of the LDC unit and an output of the filter. An output of the LDC unit is derived in dependence on the first signal received by the nonlinear function generator and the second signal output by the nonlinear function generator.

Abstract: The invention relates to a receiver (1) comprising an amplifier (31-34) for amplifying an antenna signal, which amplifier (31-34) comprises an amplifier input (11a) and an amplifier output (12a,12b), the amplifier input (11a) being a single ended input for receiving the antenna signal, the amplifier output (12a, 12b) being a differential output, and the amplifier (31-34) comprising circuit (41,42) for reducing a common mode input impedance of the amplifier (31-34).

Abstract: An amplifier has an input section with one or more input cells and an output section with one or more output cells. Either the input section or the output section includes at least two cells that may be selected to provide discrete gain settings. A loop amplifier is configured in a feedback arrangement with the input section. The input and output sections may have multiple selectable cells to provide coarse and fine gain steps. The gain of the loop amplifier may be coordinated with the gain of the input section to provide constant bandwidth operation.

Abstract: Amplifiers with power-on trim and methods using an amplifier system having an amplifier system input and an amplifier system output, an amplifier, a comparator, a successive approximation register having an input coupled to an output of the comparator, a first switch for switching an input of the amplifier from the amplifier system input to shorting the amplifier input, a second switch for switching an output of the amplifier from the amplifier system output to an input of the comparator, an output of the successive approximation register being coupled to an N bit digital to analog (D/A) converter, the D/A converter being a non-binary converter using a radix of less than 2 for at least the most significant bits, and an output of the D/A converter being coupled to the amplifier to control the input offset of the amplifier. Novel embodiments for the amplifier, comparator and D/A converter are disclosed.